Advanced Micro Devices Corporation

Jagadeesh Anathahalli Singrigowda

Girish Anathahalli Singrigowda

Prasant Kumar Vallur

Dhruvin Devangbhai Shah

Rajesh Mangalore Anand

Animesh Jain

Aniket Bharat Waghide

Prateek Mishra

Piyush Gupta

Ashish Sahu

Thanapandi Ganesan

Thanapandi G

Girish A S

A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for improving latency or power consumption

A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

High to low level shifter architecture using lower voltage devices

Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

Adaptive biasing circuit for serial communication interfaces

A high-voltage tolerant circuit includes a first level shifter responsive to an input signal having a first logic high voltage and a first logic low voltage for providing a first intermediate signal having the first logic high voltage and a second logic low voltage referenced to a second reference voltage higher than the first logic low voltage, a second level shifter responsive to the input signal for providing a second intermediate signal having a second logic high voltage referenced to a first reference voltage lower than the first logic high voltage, and the first logic low voltage, an output stage responsive to the first and second intermediate signals for providing an output signal having the first logic high voltage and the first logic low voltage, and a reference voltage generation circuit providing the second logic high and second logic low voltages without drawing current from the reference voltage generation circuit.

High-voltage tolerant inverter

A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.

Level shifting output circuit

A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

High voltage output circuit with low voltage devices using data dependent dynamic biasing

Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.

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Bengaluru, India

Jagadeesh Anathahalli Singrigowda