Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Other

Cypress Semiconductor Corportion

Jagadeesan Rajamanickam

David V James

Michael C Stephens, Jr

Dinesh Maheshwari

Sanjay M Wanzakhade

Srinivasan Venkatachary

Pradeep Kumar Bajpai

Hamid Khodabandehlou

Ajay Srikrishna

Godwin Gerald Arulappan

Stephen Henry Kolokowsky

Manaskant Dipakkumar Desai

Nimish Thakkar

Karthik Sivaramakrishnan

A USB controller includes: a USB interface that receives an isochronous timestamp packet (ITP) from a host device that includes a current time value from the host device and a delay value associated with each hub through which the ITP passed; controller hardware that initiates a counter, sends a link delay measurement (LDM) link management packet (LMP) request to a nearest upstream hub, stores a first timestamp that corresponds to when the LDM LMP request was sent, receives an LDM LMP response from the nearest upstream hub, and stores a second timestamp that corresponds to when the LDM LMP response was received; and controller software that calculates a link delay between the USB controller and the nearest upstream hub based on the first and second timestamps and delay information included in the LDM LMP response, and adjusts the counter value based on the calculated link delay.

Universal serial bus (USB) controller, method of operating a USB controller, and machine vision system

A system for transferring data files between a host device and a secondary device can include a bridge device forming at least a portion of the secondary device. The bridge device can have a de-multiplex (de-MUX) data path with an input coupled to a host interface (I/F), a first output coupled to a storage I/F and a second output coupled to a processor I/F. A controller circuit can have control inputs coupled to receive configuration commands from the processor I/F and control outputs coupled to control terminals of the de-MUX data path. The controller circuit enables and maintaining a data path between the host I/F and the first output of the de-MUX data path for a predetermined number of data transfers in response to at least a first configuration data input.

Device, method, and protocol for data transfer between host device and device having storage interface

A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system () may include encoders (and) that transmit data over signal line lanes (Laneto Lane n). In an idle state, an encoder (and) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Method and apparatus for configuring signal lines according to idle codes

An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.

Bridge device with page-access based processor interface

A search engine system () is disclosed that can include at least one content addressable memory (CAM) device () arranged in a cascade configuration with at least one memory device (), such as a static random access memory (SRAM). A CAM device () and memory device () may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (), can flow through all devices beginning with a CAM device () and eventually to a memory device (). A memory device () can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Random access memory (RAM) method of operation and device for search engine systems

A search engine method and apparatus can store and update status information for each entry of a content addressable memory (CAM) array, for a learn operation, or the like. A search engine can include a status memory block external to and independent of the CAM array. A status memory block () can include a number of memory sections (-to-) that each includes a number of bit locations for storing a free/not-free status of CAM entries in a hierarchical fashion. Corresponding control sections (-to-) can include priority encoders (-to-) that determine a first free element in a memory section for a next hierarchical level, as well as status aggregation logic (-to-) that can generate an aggregated status that is propagated to a previous hierarchical level.

Method and apparatus for learn and related operations in network search engine

According to one embodiment, a content addressable memory (CAM) device () may include a number of segments (or). Search target compare circuits (and) can compare a target value TARGET to programmable information values (PIVand PIV) associated with a particular segment (and). If a search target value TARGET matches a programmable information value (PIVand PIV), search operations may be performed in a segment (or). If a search target value TARGET does not match a programmable information value, (PIVand PIV), search operations may be prevented within a segment (or).

Content addressable memory (CAM) device having selectable access and method therefor

According to a data packet framing method of one embodiment, a data packet () may include a combination control character () that may convey framing information FLAG (-) and a code information CODE (-). Framing information FLAG (-) can indicate a start of a packet, and a code information CODE (-) can indicate another feature of a packet, such as size. A combination control character () may preferably be no larger than a data character of a data packet.

Method and apparatus for framing a data packet

According to one embodiment, a content addressable memory (CAM) device () may include a number of CAM entry sets (-and-), each of which includes multiple CAM entries. CAM () may also include multiple programmable information registers (PIRs) (-and-), each of which can be associated with a CAM entry set (-and-). PIRs (-and-) may be accessed in response to CAM commands. Values stores in PIRs (-and-) may control access to associated CAM entry sets (-and-) and/or be output in response to predetermined operations in an associated CAM entry set (-and-).

Apparatus and method for associating information values with portions of a content addressable memory (CAM) device

According to an embodiment, a content addressable memory (CAM) device () may be capable of executing a 'restricted' search operation. A restricted search operation (an 'explore' or &#x201c;search beyond&#x201d; operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Method and apparatus for restricted search operation in content addressable memory (CAM) devices

A search engine system () and CAM device () are disclosed. A search engine system () may generate response packets () in response to requests packets () and include at least one content addressable memory (CAM) device (-) having an input interface (-) for receiving data packets and an output interface (-) for transmitting data packets.

Packet based communication for content addressable memory (CAM) devices and systems

A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (-to-) in a system () having multiple branches (-and-). After chip IDs have been assigned to chips of a first branch (-) a command processing system () may issue an end of branch indication. Chip IDs may then be assigned to chips of a next branch (-).

Device identification method for systems having multiple device branches

According to one embodiment, a search engine device () may include an input (), search portion (), and a vote portion (). A vote portion () may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion () may generate an output response having its own precedence information.

Growing community of inventors

San Jose, CA, United States of America

Jagadeesan Rajamanickam