National Instruments Corporation

Jaffar Shah

Joseph E Peck

Kosta Ilic

Craig Eugene Rupp

Roman Sandoval

Audrey F Harvey

Paulo A Lamas De Anda

Zu-Yi Wang

William G Reid

Device and method for outputting a leaked radio frequency (RF) signal useable for triggering devices under test (DUTs). The device may include a vector signal analyzer (VSA) which may also perform the method for triggering DUTs. The VSA may include a first component, configured to generate an RF signal, an input configured to receive RF signals transmitted from DUTs, and a received RF signal conditioning portion, each coupled to an internal switching portion. The VSA may be configured to generate the RF signal via the first component, leak the RF signal from the first component to the internal switching portion, generating a leaked RF signal, route the leaked RF signal to the input, bypassing the received RF signal conditioning portion and output the leaked RF signal which is useable to trigger DUTs via the input.

System and method for triggering a device under test via RF leakage

A counter circuit with multiple registers for eliminating reprogramming delays and for providing seamless switching between timing signals. In a first embodiment, two registers are preloaded with values and control logic chooses between the registers for loading a counter. The counter asserts a terminal count signal to output logic, which correspondingly asserts a convert pulse to an analog measuring circuit. The control logic receives start and stop signals and the terminal count signal, where the control logic controls operation accordingly. In this manner, a delay value is initially loaded into the counter to provide an initial delay period upon receiving the start signal, and then a scan rate value is continually loaded into the counter from another register thereafter for defining the scan rate until the start signal is received. Alternatively, first and second scan rate values are preloaded into the first and second registers, respectively, and a select signal is used as a gate signal to identify which of the scan rates to use. In this manner, the scan rate is almost immediately switched to the new rate when the gate signal is toggled to achieve seamless switching. In an alternative embodiment, multiple banks of dual registers and appropriate control and select logic define a different timing signal per register bank. In each bank the two registers define the low and high durations of the respective timing signals. Thus, the frequency and duty cycle of each timing signal is fully preprogrammed and switching from one timing signal to another occurs seamlessly without delay.

Counter circuit with multiple registers for seamless signal switching

A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.

Latency error detection circuit for a measurement system

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Austin, TX, United States of America

Jaffar Shah