Apple Inc.

Qualcomm Incorporated

Marvell International Limited

Xilinx, Inc.

Rambus Inc.

Jafar Savoj

Brian S Leibowitz

Ryan D Bartling

Bruno Werner Garlepp

Hae-Chang Lee

Jaeha Kim

Emerson S Fang

Bo Sun

Sanjeev K Maheshwari

Ramy A Ahmed

Daniel J Fritchman

Kun-Yung Chang

Pierte Roo

Joseph T DiBene, Ii

Babak Soltanian

Sotirios Zogopoulos

Pradeep R Trivedi

Cheng-Hsiang Hsieh

Parag Upadhyaya

Jose A Tierno

Inder M Sodhi

Dongmin Park

Ke Yun

Gin S Yee

Praveen R Singh

Amr A Hafez

Robert S Brandt, Ii

Mansour Keramat

Cyril De La Cropte De Chanterac

Beomsup Kim

Vassili Kireev

Mazhareddin Taghivand

Sanjay Pant

Weibiao Zhang

Angelica Wong

Seyedeh Sedigheh Hashemi

Ali Mesgarani

Siok Wei Lim

Anthony Torza

Vahid Majidzadeh Bafar

Koushik Krishnan

Wayne Fang

Shah M Sharif

Cristian Marcu

Mingdeng Chen

Venkatesh B Acharya

Jun-Chau Chien

Mahmoud R Ahmadi

Mehrdad Heshami

Navin Kumar

Jasdeep S Dhaliwal

Ii Joseph T Dibene

The present disclosure describes a circuit that includes a first inductor circuit, a second inductor circuit, a first capacitor circuit, and a second capacitor circuit. The first inductor circuit includes a first inductor and a first driver circuit. The second inductor circuit includes a second inductor and a second driver circuit. The first inductor circuit operates at a first frequency. The second inductor operates at a second frequency. The first capacitor circuit provides a first signal to the second inductor circuit to adjust a first magnetic coupling generated by the first inductor circuit. The second capacitor circuit provides a second signal to the first inductor circuit to adjust a second magnetic coupling generated by the second inductor circuit.

Feedforward cancellation circuit

A current mirror circuit included in a computer system that includes a mirror stage circuit and a feedback circuit is disclosed. The mirror stage circuit generates a mirror current in an output node using a reference current. The feedback circuit adjusts the value of the mirror current based on a voltage level of the output node to increase the output impedance of the current mirror circuit.

High output impedance current mirror circuit

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

Integration of analog circuits inside digital blocks

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

Hybrid serial receiver circuit

A receiver with feed-forward equalization is disclosed. A receiver includes a delay circuit configured to receive a first signal that encodes a serial data stream having a plurality of data symbols. The delay circuit includes at least one T-coil circuit and is configured to generate a plurality of delayed signals using the first signal. The receiver further includes a front-end circuit configured to generate an equalized signal using the at first signal and one or more delayed signals of the plurality of delayed signals. A sample circuit is configured to sample the equalized signal to generate a plurality of samples. A recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.

Receiver with feed forward equalization

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The sample circuit may sample a serial data stream at different times that correspond to even-numbered and odd-numbered symbols in the serial data stream. The recovery circuit may use different coefficients to process the respective samples of the even-numbered and odd-numbered symbols in order to recover the data symbols encoded in the serial data stream.

Serial data receiver with even/odd mismatch compensation

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

Serial receiver circuit with follower skew adaptation

The present disclosure is directed to a system implementing a sensor. A sensing system is implemented in a functional circuit block that is coupled to a global supply voltage node. The sensing system includes a power converter circuit configured to generate a regulated voltage level on a local supply node using the voltage present on the global supply voltage node. The system also includes a sensor circuit coupled to receive the regulated voltage node, wherein the sensor is configured to compare corresponding parameters of different ones of a number of subset of device at a plurality of different time points and generate a plurality of comparison results. The comparisons generate an analog signal that is proportional to the operating parameter. An analog-to-digital converter (ADC) is coupled to receive the analog signal and generate a plurality of bits corresponding thereto.

Micro analog sensor circuit and system

A universally-designed control circuit for communicating with multiple types of sensors is disclosed. For example, a control circuit may communicate with either ring oscillator-based sensors or BJT-based sensors based on programming implemented in the control circuit. The control circuit may include programmable communication protocol circuits for communicating with the sensors and conversion circuits that convert a particular type of sensor data packet into a generic format. The generic format sensor data may then be utilized by a power management unit or other device to control operation of an integrated circuit.

Sensor interface circuit controller for multiple sensor types in an integrated circuit device

A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

Self referenced single-ended chip to chip communication

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

Latency reduction in analog-to-digital converter-based receiver circuits

Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.

On-chip supply ripple tolerant clock distribution

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

Low latency comparator with local clock circuit

Growing community of inventors

Sunnyvale, CA, United States of America

Jafar Savoj