Samsung Electronics Co., Ltd.

Jaeyun Lee

Daewon Kim

Junggun You

Jaehoon Shin

Bongseok Suh

Sukhyung Park

Jaejoon Han

Kyuhong Kim

Sungun Park

Sungil Park

Beomjin Park

Bongseob Yang

Jiwhan Kim

Kiho Cho

A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

Semiconductor devices including gate spacer

A processor-implemented method with image preprocessing includes: transforming a fingerprint image into a frequency domain; suppressing a low-frequency region corresponding to a first noise component of the fingerprint image in the frequency domain; and restoring the frequency domain, in which the low-frequency region is suppressed, as an image.

Method and apparatus with image preprocessing

A processor-implemented method with input data classification includes: extracting an input embedding vector including a feature of biometric information of a user from input data including the biometric information; determining an adaptive embedding vector adaptive to the input embedding vector, based on a combination of a plurality of enrollment embedding vectors that are based on enrollment data; and classifying the input data based on a similarity between the input embedding vector and the adaptive embedding vector.

Method and apparatus with input data classification

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

Integrated circuit devices having highly integrated NMOS and PMOS transistors therein and methods of fabricating the same

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Suwon-si, South Korea

Jaeyun Lee