Qualcomm Incorporated

Jaeyoung Kwak

Chi-Yuen Young

Peter S Gaal

Wanshi Chen

Tingfang Ji

Seyedkianoush Hosseini

Joseph Binamira Soriaga

Gabi Sarkis

Aamod Dinkar Khandekar

Amir Aminzadeh Gohari

Enoch Shiao-Kuang Lu

Wolfgang Roethig

Chao Jin

Methods, systems, and devices for wireless communications are described. In some systems, a base station may interrupt a user equipment (UE) during transport block (TB) encoding. The UE may cancel transmission (e.g., suppress processing) of a TB based on the interruption, such that a first subset of code blocks is encoded and a second subset is unencoded. In some cases, the UE may receive a re-transmission request for a code block including cyclic redundancy check (CRC) bits for the TB, where the CRC bits are not prepared. In one example, the UE may modify the CRC bits (e.g., set them to a common value, drop them, etc.) to reduce processing time. In another example, the base station may request re-transmission of all preempted code blocks, supporting TB CRC calculation. In another example, the base station or UE may extend a processing timeline for the re-transmission to support TB CRC calculation.

Handling transport block-level parity check bits for interrupted transmissions

Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.

Low-density parity check (LDPC) parity bit storage for redundancy versions

Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

Low-density parity check (LDPC) incremental parity-check matrix rotation

A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a plurality of data channels on a communications link, determining unused bandwidth as a difference between total bandwidth provided by the communications link and bandwidth used by the plurality of data channels, allocating the unused bandwidth to a virtual channel, scheduling the plurality of data channels and the virtual channel in accordance with a time-based multiplexing scheme, and disabling interface circuitry used to couple the transmitter to the communications link when the virtual channel is scheduled. Each of the plurality of data channels may be assigned to a source of data to be transmitted on the communications link.

Method for arbitration and adaptive power-cycling in a multi-channel network

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San Jose, CA, United States of America

Jaeyoung Kwak