Samsung Electronics Co., Ltd.

Jaeyeol Song

Sangjin Hyun

Hoonjoo Na

Dongsoo Lee

HyungSuk Jung

Jonghan Lee

Wandon Kim

Suyoung Bae

Wonkeun Chung

Jongho Park

Rakhwan Kim

Byounghoon Lee

Seungha Oh

Minjung Park

Jeonghyuk Yim

Musarrat Hasan

Hye-Lan Lee

Hyeok-Jun Son

Junehee Lee

Moonkyu Park

A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

Semiconductor device

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

Semiconductor device and method of manufacturing the same

An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

Integrated circuits and method of manufacturing the same

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

Semiconductor device having a capping pattern on a gate electrode

Gate electrode having upper and lower capping patterns

A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Semiconductor devices with gate electrodes on separate sets of high-k dielectric layers

A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate pattern on the second area. The first gate pattern includes a first gate insulating pattern on the first area, a first gate barrier pattern on the first gate insulating pattern, and a first work function metal pattern on the first gate barrier pattern. The second gate pattern includes a second gate insulating pattern on the second area, a second gate barrier pattern on the second gate insulating pattern, and a second work function metal pattern on the second gate barrier pattern. The first gate barrier pattern includes a metal material different than the second gate barrier pattern.

Semiconductor device having multiwork function gate patterns

Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Semiconductor devices and methods of manufacturing the same

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Seoul, South Korea

Jaeyeol Song