Samsung Electronics Co., Ltd.

Seoul National University

Industry-university Cooperation Foundation Hanyang University

Nanyang Technological University

Iucf-hyu (industry-university Cooperation Four

Jaewoo Park

Junghwan Choi

Youngdon Choi

Myoungbo Kwak

Younghoon Son

Joonhyung Kim

Munseong Kwon

Jueon Kim

Jinook Jung

Changsik Yoo

Youngchul Cho

Jaemoon Cha

Eunseok Shin

Hojun Yoon

Soodol Park

Wonjoo Jung

Woochul Jung

Junhan Choi

Hyolim Heo

Young Hee Choi

Donghyun Kim

Junyoung Park

Mingyu Lee

Youngsu Moon

Hyunseung Lee

Sucheol Lee

Jinwoo Cho

Yeonjoo Lee

Hyungmin Jin

Taegyoung Ahn

Yoonsik Kim

Nam Ik Cho

Minhwan Jeon

Byeongyong Ahn

Hongseok Kim

Taehyoung Kim

Youngdo Um

Duhwa Jung

Kwangseob Shin

Yongsun Lee

Jejoong Woo

Kyoungjun Roh

Jae Woong Soh

Sunjae Lim

Jungho Ko

Kwangsu Lee

Jahyun Nam

Jaeha Kim

Ikjin Jo

Junyoung Maeng

Dongmin Ko

Myoungbo Park

Meyong Su Ko

Donghyun Yoon

Uiyoon Lee

A rotary compressor includes: a case; a cylinder inside the case and has an internal space, and which includes a rolling piston configured to eccentrically rotate in the internal space, a vane in contact with the rolling piston such that while the vane is in contact with the rolling piston, the internal space of the cylinder is divided into a suction chamber and a compression chamber, a suction port to allow refrigerant to flow to the suction chamber, and a discharge port to allow the refrigerant to be discharged the compression chamber; a drive device that includes a rotation shaft connected to the rolling piston and a motor configured to rotate the rotation shaft; and a valve member that is fixed to a side surface of the vane and selectively opens and closes the discharge port as the vane reciprocates back and forth.

Rotary compressor and home appliance including same

An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.

Analog-to-digital conversion circuit and operating method of the same

According to an embodiment, an electronic device may comprise: at least one communication processor, an RF circuitry connected to the at least one communication processor, and a plurality of antennas connected to the RF circuitry. The at least one communication processor may be configured to, based on identifying a folding state of the electronic device being an open state, control the RF circuitry to provide a first RF signal corresponding to a first frequency band to a first antenna among the plurality of antennas. The at least one communication processor may be configured to, based on identifying the folding state of the electronic device being a closed state, identify whether the electronic device is gripped. The at least one communication processor may be configured to control the RF circuitry to provide a second RF signal corresponding to the first frequency band to a second antenna different from the first antenna among the plurality of antennas, based on identifying that the electronic device is gripped.

Electronic device changing transmission antenna and method for operating the same

A receiver for receiving a data signal, comprising, an analog-to-digital converter configured to convert the data signal into digital data, a first-in-first-out buffer configured to determine a frame boundary of the digital data by referring to a comma index to output the digital data in units of data frames according to the determined frame boundary, a decision feedback equalizer configured to process a data frame output from the first-in-first-out buffer through a decision feedback equalization operation, wherein feedback data used in the decision feedback equalization operation of the data frame uses a predetermined fixed pattern, and a comma detector configured to generate the comma index by comparing a determined value of the data frame with the predetermined fixed pattern. The data frame may include a preceding data field in which a message is stored and a subsequent comma field having the same bit value as the fixed pattern.

Equalizers, communication systems and operating methods thereof

A receiver includes a voltage-to-time converter configured to sequentially output a first converted signal and a second converted signal based on a first signal, a second signal, and a time difference; a first time comparator configured to determine a first bit value based on a first first-arrival signal (FAS) and output first data including the first bit value; a delay time generator configured to select a non-target signal and a target signal based on the first bit value and from among the first converted signal and the second converted signal; and a second time comparator configured to determine a second bit value based on a second FAS and output second data including the second bit value.

Receiver, operation method thereof, and memory device

A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

Transmitter for ultra-high speed and storage device including the same

A hermetic compressor including a casing; a motor inside the casing, and including a rotor and stator; a drive shaft that rotates with the rotor; a compression unit below the motor to compress refrigerant and discharge compressed refrigerant to an inside of the casing; and an oil blocking guide above the motor to rotate with the rotor. The oil blocking guide includes an oil blocking plate formed in a disk shape, an oil guide part extending outward and upward from an edge of the oil blocking plate, and a support part connecting the oil blocking plate to the drive shaft and space the oil blocking plate from the rotor. The oil blocking plate and the oil guide part block upward movement of oil passing through the motor, and guide the oil to an inner circumferential surface of the casing through centrifugal force while the oil blocking guide is rotating.

Hermetic compressor with oil blocking guide

An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

Apparatuses and methods for timing skew calibration

An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

Electronic devices converting input signals to digital value and operating methods of electronic devices

A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.

Digital phase locked loop and methods of operating same

A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.

Quadrature error correction circuit and semiconductor memory device including the same

A rotary compressor includes a rotary shaft rotating in a first direction and defining each of an oil channel along which oil moves, an oil hole corresponding to a cylinder and a gas hole above the cylinder, and an oil paddle rotating in the first rotation direction together with the rotary shaft, the oil paddle including a first length region twisted in a second rotation direction opposite to the first rotation direction, and a second length region twisted in the first rotation direction, where rotation of the rotary shaft in the first rotation direction includes the first length region of the oil paddle transferring the oil along the oil channel and toward the gas hole, together with the second length region of the rotary shaft transferring the oil along the oil channel and away from the gas discharge hole.

Rotary compressor and home appliance including the same

The disclosure relates to a compressor having a noise reduction resonator. The compressor includes: a compression part having compression space in which introduced gas is accommodated, and configured to compress and discharge the gas in the compression space; and a gas moving part having an inner wall forming a gas flow path through which the gas discharged from the compression space moves, wherein the gas moving part is provided with a first resonator configured to communicate with the gas flow path on the inner wall forming the gas flow path and having a resonance space depressed upward in a moving direction of the gas. The compressor according to the disclosure may prevent compression efficiency from decreasing and maintain a noise reduction effect for a long period of time by preventing foreign objects or liquids from being accumulated in the resonance space.

Compressor and electronic device using the same

According to various embodiments, an electronic device may comprise: at least one antenna, a plurality of radio frequency (RF) devices configured to perform generation of a transmission RF signal input to the at least one antenna and/or conversion of a reception RF signal output from the at least one antenna, and at least one processor. The at least one processor may be configured to: detect an error in at least one RF device among the plurality of RF devices, identify at least one RF path associated with the at least one RF device with the error and at least one frequency associated with the at least one RF path, adjust a user equipment (UE) capability supported by the electronic device, by modifying and/or deleting an information element associated with the at least one frequency among at least one information element of the UE capability, based on the at least one RF path, and report the adjusted UE capability to a network.

Electronic device managing UE capability and method for operating the same

A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

Parallel-to-serial interface circuit and transmission device having the same

Growing community of inventors

Yongin-si, South Korea

Jaewoo Park