Samsung Electronics Co., Ltd.

Jaewon Park

Daewon Kim

Jiyoung Han

Hyosang Bang

Hyun Yeul Lee

Youngseong Kim

Insheik Martin Jung

Hyungmin Kim

Hyunyeul Lee

Soeyoun Yim

Junho Lee

Eunsil Lim

Shinhaeng Kang

Jaehoon Lee

Yongkoo Lee

Sukhan Lee

Hyemi Yu

Sookkyung Lee

Seungkyung Lim

Seonggu Jeon

Misook Yu

Ahrem Nam

Sangkil Park

Haemi Yu

Display screen or portion thereof with transitional graphical user interface

Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.

Memory device and test method of memory device

A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

Built-in self-test circuits for memory systems having multiple channels

Display screen or portion thereof with graphical user interface

A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

Method of testing memory device, memory built-in self test (MBIST) circuit, and memory device for reducing test time

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Seoul, South Korea

Jaewon Park