Oracle America, Inc.

Jaewon Oh

Krishnan Sundaresan

Robert E Mains

Venkatesh P Gopinath

Wei-Lun Hung

Ke Peng

A method for computing power consumption includes querying a software database for a key node and a gate comprising an input port, connected to the key node, and an output port. The software database is created from a net list associated with a design. The method includes calculating a probability of activity level at the output port based on a predetermined activity level at the key node, and querying the software database for next gate comprising a next input port, connected to the previous output port, and a next output port. The method includes calculating a probability of activity level at the next output port based on the probability of activity level at the previous output port. The method includes computing a sub-circuit gate power by sum of power of all the gates based on the probability of activity level at output ports of the gates.

Technique for fast power estimation using probabilistic analysis of combinational logic

Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.

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Cupertino, CA, United States of America

Jaewon Oh