Electronics and Telecommunications Research Institute

Jaewon Nam

Young Kyun Cho

Jong-Kee Kwon

Young-Deuk Jeon

Yil Suk Yang

Hui Dong Lee

Jongdae Kim

Minki Kim

Jimin Oh

Yil Suk Yamg

A motor control device including a preprocessing portion calculating a counter electromotive force using an analog operation is provided. The motor control device may include an offset compensation portion and a counter electromotive force measuring portion. The offset compensation portion receives a three-phase current signal from the motor and compensates an offset of the three-phase current signal. The counter electromotive force measuring portion receives the compensated current signal and a three-phase voltage signal from the motor and calculates the received current signal and the received voltage signal using an analog operation to provide the calculated result.

Motor control device and method of controlling the same

Disclosed is a power control driving device which includes a sine wave signal generating unit; a control signal converting unit configured to convert a sine wave from the sine wave signal generating unit into a multi-bit control signal; and a three-phase inverter circuit configured to output a voltage varied by the multi-bit control signal from the control signal converting unit. The control signal converting unit includes a multi-bit sigma-delta modulator configured to convert an analog sine wave into a digital signal. The three-phase inverter circuit includes a plurality of switch units, on-off states of the plurality of switch units being controlled according to the multi-bit control signal from the control signal converting unit.

Apparatus and method for reducing a noise in an output waveform using a multi-bit sigma-delta modulator and a three phase inverter

Provided is a sensorless BLDC motor system. The sensorless BLDC motor system includes a BLDC motor, a comparator, a motor controller, a three-phase inverter, and a mode selector. The BLDC motor includes first to third coils. The comparator compares a voltage of a specific coil of the first to third coils with a neutral-point voltage to output the compared result. The voltage of the specific coil becomes equal to the neutral-point voltage and a specific time elapses, and then the motor controller generates first and second coil control signals based on the compared result. The three-phase inverter supplies a source voltage or ground voltage to the specific coil, or floats the specific coil, in response to the first and second coil control signals. The mode selector selects a driving mode of the BLDC motor by adjusting the specific time.

Sensorless BLDC motor systems and driving methods of sensorless BLDC motor

An analog to digital converter in accordance with the inventive concept may include a reference voltage generation circuit outputting first and second reference voltages; a decompression part decompressing amplitude of an analog input signal and the first and second reference voltages; a flash ADC converting the decompressed analog input signal into a first digital signal with reference to the decompressed first and second reference voltages; and a successive approximation ADC converting the analog input signal into a second digital signal according to a successive approximation operation with reference to the first digital signal and the first and second reference voltages.

Mixed mode analog to digital converter and method of operating the same

A delay time control circuit is provided which includes a delay locked loop generating a second clock signal delayed by a predetermined time in response to a first clock signal; a plurality of delay circuits each receiving the first and second clock signals and outputting third and fourth clock signals in response to first and second digital clock signals; and a feedback control unit receiving the third and fourth clock signals to detect a delay time and generating the first and second digital control signals for compensating the detected delay time.

Delay time control circuit and control method thereof

Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.

Analog-digital converter and power saving method thereof

Disclosed is a triangular wave generator which includes a square wave signal generating unit configured to output a first signal transitioning to a high level from a low level via an output terminal in response to a first transition of a clock signal and to transition the first signal to a low level from a high level in response to a reset signal; a resistance unit configured to adjust a voltage level of a the square wave signal; and a capacitance unit configured to receive an output signal of the resistance unit to generate a second signal rising to a high level from a low level with a slope, to provide the reset signal to the square wave signal generating unit, and to output a triangular signal by falling the second signal to a low level from a high level with a slope.

Triangular wave generator and method generating triangular wave thereof

A pipelined analog-to-digital converter includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.

Pipelined analog digital convertor

Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

Analog digital converter

Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.

Pipelined analog digital converter

Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

Growing community of inventors

Daejeon, South Korea

Jaewon Nam