Samsung Electronics Co., Ltd.

JaeWha Park

Dongchan Lim

Sukhoon Kim

Moonkeun Kim

Jaejin Lee

Sanghoon Ahn

Kyu-Hee Han

Hana Kim

Jun Kwan Kim

Heesook Park

A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

Semiconductor device including gate structure having first portion and second portion and method for manufacturing the same

A wiring structure includes a filling metal, a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal, a barrier metal on an outer surface of the first portion of the cover metal, and a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, wherein the filling metal has higher conductivity than the cover metal and the barrier metal.

Wiring structure having double capping structure, manufacturing method thereof, and integrated circuit chip having the same

Method for manufacturing a semiconductor device using a support layer to form a gate structure

Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

Semiconductor device

Growing community of inventors

Yongin-si, South Korea

JaeWha Park