Samsung Electronics Co., Ltd.

Jaeuk Ahn

Jinyong Kim

Youngkyu Kim

Donghee Kim

Serhoon Lee

Junhwan Lee

Changok Lim

Jinwoo Hwang

Homin Kang

An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

Image signal processor and image processing system performing interrupt control

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Suwon-si, South Korea

Jaeuk Ahn