Motorola Corporation

Other

Jaeshin Cho

Gregory L Hansell

Bruce A Bernhardt

Jonathan K Abrokwah

Kelly Wayne Kyler

Naresh C Saha

Mark A Durlam

Jenn-Hwa Huang

Schyi-Yi Wu

Wayne A Cronin

Fred Reece Clayton

Craig L Jasper

James H Williams

A process for improving uniformity across the surface of a substrate during a plasma process such as plasma etching. A conductive plane is formed at the back surface of the substrate. A plasma process is then performed to the front surface of the substrate. The conductive plane may then be removed upon completion of the plasma process and before final processing steps.

Plasma processing method

An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Method of forming an ohmic contact to a III-V semiconductor material

An etch stop layer prevents damage to the underlying semiconductor material or metallization layer during etching of a dielectric layer overlying the etch stop layer. The etch stop layer, aluminum nitride or aluminum oxide is used underlying silicon dioxide to prevent damage to the semiconductor material during a fluorocarbon based etch of the silicon dioxide. The etch stop layer is also used underlying a silicon dioxide layer and overlying a titanium nitride or titanium tungsten layer used in metallization to prevent etching of the titanium nitride or titanium tungsten layer during etching of the silicon dioxide.

Method utilizing an etch stop layer

A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

III-V semiconductor gate structure and method of manufacture

A III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Self-aligned FET having etched ohmic contacts

A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Method of manufacture of multilayer dielectric on a III-V substrate

Method of manufacturing a III-V semiconductor gate structure

The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.

Method of making ohmic contacts to a complementary III-V semiconductor

The present invention provides a III-V semiconductor FET (10, 30, 40) having etched ohmic contacts (19, 20, 36, 37, 43, 44). A gate (16) of the FET (10, 30, 40) is formed in contact with a surface of a III-V substrate (11). An ohmic contact (19, 20, 36, 37, 43, 44) is created to include an alloy in contact with the surface of the substrate (11). The ohmic contact (19, 20, 36, 37, 43, 44) is formed to abut the gate structure (16, 17, 18) by covering a portion of the gate structure (16, 17, 18) and the substrate (11) with the ohmic contact (19, 20, 36, 37, 43, 44), then, removing portions of the ohmic contact from the gate structure (16, 17, 18) by etching. The ohmic contact (19, 20, 36, 37, 43, 44) is formed to be substantially devoid of gold.

Method of forming a GaAs FET having etched ohmic contacts

The present invention includes forming an etched ohmic contact (10, 9) by applying a layer of an etch susceptible contact material (14) to a III-V semiconductor substrate (11). A portion of the contact layer (14A) is alloyed with the substrate (11) to form are etch resistant area (14A) of the contact layer. The contact layer (14) is selectively etched to remove etch susceptible portions of the contact layer while leaving the etch resistant area (14A) on the substrate (11). Another alloy operation is performed to form ohmic contact between the etch resistant area (14A) and the substrate (11). Consequently, an etch ohmic contact (10, 9) that is substantially devoid of gold is formed.

Method of forming an etched ohmic contact

A method for making a shallow junction in a gallium arsenide substrate including implanting doping ions into an upper surface of the substrate and incorporating sulfur into the upper surface of the substrate after the ion implantation. A capping layer is deposited on the upper surface and the substrate is heat annealed to activate the doping atoms.

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Gilbert, AZ, United States of America

Jaeshin Cho