Samsung Electronics Co., Ltd.

Jaeseung Choi

Hyunchang Shin

Songhee Jung

Yongkoo Her

Joongyu Lee

Youngdo Kim

Jungbae Bae

Hyunsu Choi

Byungduk Yang

Dong-Wook Seo

Gyuhong Kim

Various embodiments disclose a method and an apparatus including a display, a memory including information on a number of duty cycles per one refresh period for emitting light by pixels of the display corresponding to each of a plurality of refresh rates of the display, and a processor, wherein the processor is configured to control the electronic device to perform an operation according to a first number of duty cycles based on the display operating at a first refresh rate, and perform an operation according to a second number of duty cycles based on the display operating at a second refresh rate, wherein the first number is less than the second number based on the first refresh rate being higher than the second refresh rate.

Apparatus and method for driving display based on frequency operation cycle set differently according to frequency

Disclosed is an electronic device. An electronic device according to various embodiments may include an optical sensor and a display panel. The display panel may include a first substrate, a second substrate, a pixel layer disposed between the first substrate and the second substrate, the pixel layer having at least one opening in at least a portion thereof, and a light-transmissive member comprising a light-transmissive material disposed in at least a portion of the opening and having a second reflective index corresponding to a first reflective index of the second substrate. The optical sensor may be disposed below the second substrate and at least partially overlap a predetermined area of the display panel corresponding to the opening.

Electronic device including sensor mounted below display panel

A display device is provided. The display device includes a display driver circuit, and a display panel including a display area including a plurality of pixels, a non-display area, an empty area enclosed by the plurality of pixels, a first scan driving circuit disposed in a first partial area of the non-display area formed outside of a first side of the display area, at least one first scan line extended towards the empty area from the first scan driving circuit, a second scan driving circuit and disposed in a second partial area of the non-display area formed outside a second side adjacent to the first side of the display area, and at least one second scan line extended towards the empty area from the second scan driving circuit to be connected to at least one second pixel of the plurality of pixels.

Display device including scan driver for driving display panel in which empty area enclosed by display area is formed

A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

System on chip including dual power rail and voltage supply method thereof

A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode.

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Suwon-si, South Korea

Jaeseung Choi