Samsung Electronics Co., Ltd.

Jaerok Kahng

Jungwoo Song

Yongjun Kim

Keeshik Park

Jinwoo Lee

Jaekyu Lee

Joon-Seok Moon

Sang-Jun Lee

Dong-Soo Woo

Donggyun Han

Taehong Ha

A variable resistance memory device includes lower conductive lines on a substrate, upper conductive lines on the lower conductive lines to cross the lower conductive lines, and memory cells between the lower conductive lines and the upper conductive lines. The lower conductive lines are extended in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the lower conductive lines include a first line portion extended in the first direction, a second line portion offset from the first line portion in the second direction and extended in the first direction, and a connecting portion connecting the first line portion to the second line portion.

Variable resistance memory device

A semiconductor device includes active pillars protruding from a semiconductor substrate and spaced apart from each other in a first direction and a second direction that is perpendicular to the first direction, a word line extending in the first direction between the active pillars, a drain region disposed in an upper portion of each of the active pillars, and a separation pattern provided between the word line and the drain region. A bottom surface of the separation pattern is disposed at a lower level than a bottom surface of the drain region.

Semiconductor device and method of fabricating the same

A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.

Memory device having buried gate and method of fabricating the same

Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.

Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer

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Seoul, South Korea

Jaerok Kahng