Samsung Electronics Co., Ltd.

Jaepil Lee

Sungjin Kim

Seok-ho Shin

Joodong Kim

Dongwon Lim

Bonhwi Gu

Hyekyeong Kweon

Minhee Cho

Hijung Kim

Kwangchol Choe

Kwangsook Noh

A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.

Transistor structure including oxide semiconductor pattern surrounding bottom and sidewall of gate and semiconductor device using the same

A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Memory device, memory system having the same, and method of operating the same

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

Semiconductor device

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Seoul, South Korea

Jaepil Lee