Apple Inc.

Jaemyung Lim

Mohamed Hassan Abu-Rahma

Jaroslav Raszka

Shahzad Nazar

Raghuram C Kamath

Iyappan Ramachandran

Mohammad Shokoohi-Yekta

Shawn Searles

Victor Zyuban

Michael A Dreesen

Harneet Singh Oberoi

Hameet Singh Oberoi

Jacek R Wiatrowski

Jiangyi Li

In some embodiments, an electronic device performs an action in response to detection of a sequence of one or more motion gestures. Motion gesture information of a first electronic device optionally includes a first portion representing a respective attitude of the first electronic device relative to a frame of reference and a second portion that includes movement of the first electronic device from the respective attitude of the first electronic device. In accordance with a determination that the movement of the first electronic device during the second portion of the motion gesture meets movement criteria for a movement gesture that corresponds to the respective attitude of the first electronic device, a process is initiated to control the first electronic device or a second electronic device in accordance with the second portion of the motion gesture.

System and method of controlling devices using motion gestures

An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.

Amplifier offset cancelation

A memory array that provides an internal retention voltage without a voltage regulator is disclosed. The memory array includes a first group of bit cells coupled between the power supply rail and a ground switch and a second group of bit cells coupled to a retention select circuit. The retention select circuit is coupled to the ground for the first group of bit cells and the power supply rail. The ground switch and the retention select circuit may be operated to switch the bit cells between a nominal operating voltage and a retention voltage. The retention voltage is provided during inactive periods of the memory array to maintain data in the bit cells during the inactive periods.

Sram bit cell retention

Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.

Retention voltage generator circuit

Computer systems may include multiple power switch circuits for coupling circuit blocks to power supply signals. Different power supply signals may be selected for use in the generation a control signal for a power switch device in the power switch circuit. For example, during a particular operating mode of a power switch circuit coupled to a circuit block, a power supply signal with a voltage level greater than an power supply signal for the circuit block may be used to generate the control signal.

Low leakage power switch

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Sunnyvale, CA, United States of America

Jaemyung Lim