Samsung Electronics Co., Ltd.

Sungkyunkwan University

Jaemin Choi

Changsik Yoo

Yonghun Kim

Yoochang Sung

Daehyun Kwon

Buyeon Lee

Jaewoo Jeong

Jeongdon Ihm

Kyungryun Kim

Chisung Bae

Jaesang Lee

Hyun Suk Jung

Jung-Hoon Chun

Jaesung Kim

Yoonmyung Lee

Jin Hyuk Choi

Jonghan Kim

Jae Myeong Lee

Jinhyeok Baek

Saein Suh

Gil Sang Han

Hee Jung Kim

The present application relates to a method for manufacturing an inverse opal structure membrane filter, the method comprising the steps of: preparing a mixed solution by mixing a nanoparticle dispersion solution and a sacrificial particle dispersion solution; applying the mixed solution onto a substrate to dry it; and heat-treating the mixed solution, wherein the surface of the sacrificial particles is modified by positive charges or negative charges.

Preparing method of membrane filter including inverse opal structure

A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same

A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

Memory devices, memory systems having the same, and operating methods thereof

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Interface circuit and operating method thereof to compensate for supply voltage variations

A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

Data receiving devices, memory devices having the same, and operating methods thereof

An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.

Low power RC oscillator with switched bias current

Growing community of inventors

Suwon-si, South Korea

Jaemin Choi