Samsung Electronics Co., Ltd.

Jaekyung Yoo

Yeongkwon Ko

Teak Hoon Lee

Jayeon Lee

Teakhoon Lee

Jae-Eun Lee

Un-Byoung Kang

Jin-woo Park

Jaeeun Lee

Jin-Woo Park

Jinwoo Park

Jongho Lee

Chungsun Lee

Unbyoung Kang

Myungsung Kang

A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.

Molding apparatus of semiconductor package

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Semiconductor package and method of fabricating the same

A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

Semiconductor package

A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

Semiconductor package including mold layer and manufacturing method thereof

A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

Semiconductor package including part of underfill on portion of a molding material surrounding sides of logic chip and memory stack on interposer and method for manufacturing the same

Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

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Seoul, South Korea

Jaekyung Yoo