Korea Advanced Institute of Science and Technology

Skhynix Inc.

Link a Media Devices Corporation

Sk Hynix Memory Solutions Inc.

Jaekyun Moon

Younghyun Park

Jun Hyuk Seo

Beongjun Choi

Sung Whan Yoon

Sang Chul Lee

Sang Sik Kim

Joong Seob Yang

Ho Yeon Lee

Sang Ho Yun

Suk Kwang Park

Hemant Thapar

Seok Hwan Choi

Soon-Young Kang

Jun Beom Seo

Hernant Thapar

Jy Yong Sohn

Geunyeong Yu

Dong-Jun Han

Soonyoung Kang

Seung Ho Chang

Jungwuk Park

Jaehyeong No

Sunyoung Jo

Minsu Choi

Sung-Whan Yoon

Seongwook Jeong

An object detecting device includes a feature extracting circuit configured to extract first feature data from an input image; a feature transforming circuit configured to transform the first feature data into transformed feature data according to a transformation function; and a decoder circuit configured to decode the transformed feature data into a region map indicating a detected object.

Device for detecting an object using feature transformation and method thereof

An edge detecting device includes a feature extracting circuit configured to extract first and second feature data from an input image; a prototype generating circuit configured to generate prototype data using the first feature data and an input label, the prototype data including foreground and background information of an object; a region detecting circuit configured to generate a segmentation mask by detecting a region of an object using the first feature data and the prototype data; and an edge extracting circuit configured to generate an edge map by combining the segmentation mask and the second feature data.

Device for detecting an edge using segmentation information and method thereof

A device includes a threshold voltage distribution estimation network configured to generate an estimated distribution using a feature distribution and read trial information, a set of feature distributions generated from a plurality of threshold voltage distributions for a plurality of pages of a memory device, and a read reference voltage estimation network configured to generate a read reference voltage from the estimated distribution. The read trial information includes a read trial vector and an output value, the output value being generated by applying the read trial vector to a threshold voltage distribution for a page to be read among the plurality of threshold voltage distributions.

Device for determining read reference voltage of a memory device and operating method thereof

A data processing method by learning of a neural network may be provided. The data processing method by the learning of a neural network includes: obtaining a first set of output values by processing a first set of input values of a task by the neural network; forming a projection space on the basis of the first set of output values; obtaining a second set of output values by processing a second set of input values out of input values of the task by the neural network; projecting the second set of output values onto the projection space; and performing processing the second set of output values in the projection space.

Data processing apparatus by learning of neural network, data processing method by learning of neural network, and recording medium recording the data processing method

A method for transmitting agreed data on a network by an electronic apparatus, the method according to an embodiment of the present invention may include the steps of storing a generation matrix generated on the basis of the number of a plurality of electronic apparatuses including the electronic apparatus participating in the network and the number of a plurality of data blocks to be shared between the plurality of electronic apparatuses and transmitting an agreed data block agreed to be shared with another electronic apparatuses included in the plurality of electronic apparatuses to another electronic apparatus on the basis of the generation matrix.

Agreed data transmit method and electronic apparatus for transmitting agreed data in network

A memory system includes a memory device including a plurality of memory cells, and a controller configured to access the plurality of memory cells. The controller includes a data read block configured to read first data from one or more pages included in first memory cells, determine a target memory cell subject to a compensation based on the first data, and read second data from one or more pages of second memory cells adjacent to the target memory cell, and an equalizer configured to convert the second data into symbol interfering data, check a probability of the first data from a lookup table according to the symbol interfering data, and determine the compensation on the first data based on the probability.

Memory system for interference compensation and operating method thereof

A controller may include a first encoder suitable for generating a first polar parity by performing a first polar encoding operation to respective first sections of an original message having a plurality of symbols, an interleaver suitable for generating an interleaved message by interleaving the original message according to first reliabilities, which are predetermined depending on locations of the respective symbols in the respective first sections in the original message, and second reliabilities, which are predetermined depending on locations of the respective symbols in the interleaved message, a second encoder suitable for generating a second polar parity by performing a second polar encoding operation to respective second sections included in the interleaved message and a memory interface suitable for storing the original message, the first polar parity and the second polar parity into a memory.

Controller and operating method thereof

An operation method of a controller includes: generating a predetermined number of sub-messages by dividing an original message; generating a first parity added message by adding a cyclic redundancy check (CRC) parity message of a predetermined length to each of the sub-messages; and generating an encoded message by performing a polar encoding operation to the first parity added message.

Controller, semiconductor memory system and operating method thereof

A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.

Concatenated error correction device

Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.

Method of decoding LDPC code for producing several different decoders using parity-check matrix of LDPC code and LDPC code system including the same

A method for estimating channel characteristics of a nonvolatile memory device including a plurality of memory cells includes the steps of: calculating first threshold voltage distributions of the memory cells programmed according to input data, based on the input data and a physical structure of the memory cells; calculating second threshold voltage distributions of the memory cells, based on output data and the physical structure of the memory cells; and analyzing the relation between the first and second threshold voltage distributions, using a mask.

Method for estimating channel characteristics of nonvolatile memory device

f(x(s, s))=A(s)+B(s) is calculated for npairs of consecutive state variables {s, s} using A(s)=min{A(s)+&#x393;(x=x)} and B(s)=min{B(s)+&#x393;(x=x, s)}, where &#x393;(x=x) is a metric associated with a branch x=x connecting consecutive state variables sand s. The nlowest values are selected from the ncalculated values of f(x(s, s))=A(s)+B(s) and log likelihood ratios (LLRs) are set to those lowest f(x(s, s)) values. The nvalues of x that correspond to the nlowest values are determined.

Low-complexity q-ary LDPC decoder

A signal is encoded by receiving input data. A first portion of the input data is encoded to obtain a first set of encoded data. At least some part of the input data is processed to determine which one of a plurality of subsets the input data corresponds to. In the event the input data corresponds to a first subset having a greater signal margin (SM) than a second subset, the first set of encoded data and a second portion of the input data are output. In the event the input data corresponds to the second subset, the second portion of the input data is encoded to obtain a second set of encoded data and the first set of encoded data and the second set of encoded data are output.

Set partitioning and multilevel coding

A probability is determined, including by obtaining a set of probability ratios, wherein each probability ratio in the set is a ratio of a first probability to a second probability. A probability P(E=z) that an merror symbol Ehas a level of z is determining based at least in part on one or more dominant error patterns.

Growing community of inventors

Daejeon, South Korea

Jaekyun Moon