Micron Technology Incorporated

Intel Corporation

Jaekwan Park

Feng Q Pan

Ramin Ghodsi

Michele Piccardi

Kalyan C Kavalipurapu

Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

Apparatuses and methods for segmented SGS lines

A memory device includes a conductive line coupled to access addressable storage locations of the memory device. The memory device includes a circuit with a line driver with an access device for the conductive line. A control circuit sets a gate of the access device to an initial overdrive bias voltage to drive a drain of the access device to an initial voltage while the access device control circuit is not connected to the conductive line via another conductive line. The control circuit floats the gate voltage of the access device and connects the control circuit to the conductive line via the other conductive line. The floating initial overdrive voltage does not drop when the initial voltage of the control circuit drops to a final voltage under load conditions. The overdrive can result in a steeper program slope, and a controllable program pulse width or programming time (t).

Floating block select based programming time (tPROG)

Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Methods and apparatuses for compensating for source voltage

Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source cooled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node or the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memory subblocks.

Growing community of inventors

Cupertino, CA, United States of America

Jaekwan Park