Samsung Display Co., Ltd.

Samsung Displayco., Ltd.

Jaekeun Lim

Jinyoung Roh

Hyojin Lee

Sehyuk Park

Hongsoo Kim

Chongchul Chai

Bon-seog Gu

Hae-kwan Seo

Jonghee Kim

Youngwan Seo

Bonghyun You

Taehoon Kim

Sangan Kwon

Ji-Sun Kim

Hui Nam

Junhyun Park

Soon-Dong Kim

Donggyu Lee

Changnoh Yoon

Kyoungju Shin

Jin-wook Yang

Soon-dong Kim

Sunghwan Kim

Bong-Hyun You

Hee-keun Lee

Yeun Tae Kim

Oh Jo Kwon

Yu-chol Kim

Jae-hyeon Jeon

Woomi Bae

Jiwoong Kim

Hyungryul Kang

Jiyoun Kim

Yoshimura Hideo

Hyunjoon Kim

Hae-Kwan Seo

Cheol-Gon Lee

Dong Won Lee

Geunjeong Park

Cholho Kim

Heesoon Jeong

Joon-chul Goh

Youngha Sohn

JeonKyoo Kim

Jisun Kim

Junheyung Jung

Seyoung Song

Se-hyang Kim

Jeongkyoo Kim

A display device includes: a first light emitting element; a third light emitting element adjacent to the first light emitting element in a first direction; second light emitting elements respectively adjacent to the first and third light emitting elements in a second direction crossing the first direction; first pixel circuits respectively under the first and third light emitting elements; second pixel circuits respectively under the second light emitting elements; and a dummy pixel circuit in a dummy circuit area adjacent to a display area in which the first, second, and third light emitting elements and the first and second pixel circuits are arranged and connected to the third light emitting element, wherein the dummy pixel circuit has a width smaller than a width of each of the first pixel circuits in the second direction.

Display device

A display panel is disclosed that includes 2-1 to 2-4 pixel circuit sequentially disposed in a first direction in a second pixel row and 2-1 to 2-4 light emitting area sequentially disposed in the first direction. The 2-1 pixel circuit is connected to a first data line, the 2-2 pixel circuit is connected to a second data line, the 2-3 pixel circuit is connected to a third data line and the 2-4 pixel circuit is connected to a fourth data line. The 2-1 pixel circuit is connected to the 2-3 light emitting area, the 2-2 pixel circuit is connected to the 2-1 light emitting area, the 2-3 pixel circuit is connected to the 2-2 light emitting area and the 2-4 pixel circuit is connected to the 2-4 light emitting area. A color of the 2-1 light emitting area is different from a color of the 2-3 light emitting area.

Display panel

A display panel of a display device includes: first to fourth pixel circuits connected to first to fourth data lines, respectively; first to fourth light emitting elements for emitting light of different colors; a first connection line for connecting the first light emitting element to the second pixel circuit; a second connection line for connecting the second light emitting element to the first pixel circuit; a third connection line for connecting the third light emitting element to the fourth pixel circuit; and a fourth connection line for connecting the fourth light emitting element to the third pixel circuit.

Display panel and display device including the same

A display device includes a display panel including a pixel including a pixel circuit and a light emitting element, a plurality of scan lines connected to the pixel circuit, an emission control line connected to the pixel circuit, and a data line connected to the pixel circuit. The pixel circuit includes a first capacitor connected to a first node and a second node opposite to the first node, a first circuit portion that includes a first transistor connected between the data line and the first node and a second transistor connected between the first transistor and the first node, and a second circuit portion connected to the second node and the light emitting element. Before the light emitting element emits light, a reference voltage is provided to a third node between the first transistor and the second transistor.

Display device operated in single frequency mode and multi-frequency mode

A shift register includes a plurality of stages. At least one of the stages is configured to receive an input signal, a first clock signal, a second clock signal, a first power voltage and a second power voltage and to output an output signal. The at least one of the stages includes a pull up switching element connected between a first power voltage terminal configured to receive the first power voltage and an output terminal configured to output the output signal, a pull down switching element connected between a second power voltage terminal configured to receive the second power voltage and the output terminal, a first pull down control switching element connected to a control electrode of the pull down switching element and a second pull down control switching element connected to the first power voltage terminal and the control electrode of the pull down switching element.

Shift register and display apparatus including the same

A display panel includes 11-th to 15-th pixel circuits arranged in a first row, 21-th to 25-th pixel circuits arranged in a second row, 11-th to 14-th light-emitting elements, each being connected to corresponding one of the 11-th to 15-th pixel circuits, and 21-th to 24-th light-emitting elements, each being connected to corresponding one of the 21-th to 25-th pixel circuits. The 11-th light-emitting element is connected to one of the 11-th to 15-th pixel circuits overlapping therewith, wherein the 13-th light-emitting element is connected to one of the 11-th to 15-th pixel circuits non-overlapping therewith via a first connection wiring, wherein the 21-th light-emitting element is connected to one of the 21-th to 25-th pixel circuits overlapping therewith, wherein the 23-th light-emitting element is connected to one of the 21-th to 25-th pixel circuits non-overlapping therewith via a second connection wiring.

A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Pixel and display device capable of operating at high operating frequency

A display device includes a display panel, a scan driver outputting a scan signal, and a data driver. The scan driver includes a first sub-scan driver that receives a first start signal and an odd clock signal, and a second sub-scan driver that receives a second start signal and an even clock signal. The scan signal has an activation period corresponding to a horizontal period. The odd clock signal includes a first clock enable period and a first clock disable period, which are 'k' times greater than the horizontal period. The even clock signal includes a second clock enable period and a second clock disable period, which are ‘k’ times greater than the horizontal period. The first clock enable period and the second clock enable period alternate with one another.

Display device including scan driver controlled by clock signals

A display panel driving circuit includes a scan driving circuit including a scan stage and a timing controller. The scan stage includes a first circuit connected to a first input node of receiving a first clock signal, a second circuit connected to a second input node of receiving a second clock signal, a third circuit connected to a third input node of receiving a carry signal, the first circuit, and the second circuit and connected to a first control node and a second control node, a pull-up transistor electrically connected to the first input node and an output node of outputting a scan signal and turned on/off by the first control node, and a pull-down transistor electrically connected to the output node and a low-level voltage line and turned on/off by the second control node.

Display panel driving circuit and display device including the same

A display apparatus includes a display panel, a gate driver, a data driver, a driving controller and a power voltage generator. The display panel displays an image based on input image data. The gate driver outputs a gate signal to a gate line. The data driver outputs a data voltage to a data line. The driving controller drives display areas of the display panel in different driving frequencies. The power voltage generator outputs a data power voltage to the data driver. The driving controller outputs an output data enable signal including a writing period having an active signal and a holding period having an inactive signal for the respective display areas. The power voltage generator generates the data power voltage having a high power voltage level during the writing period and a low power voltage level in at least a portion of the holding period.

Display apparatus and method of driving display panel using the same

A display panel of a display device includes: first light emitting elements located in a first row, second light emitting elements located in a second row adjacent to the first row, first pixel circuits located in the first row, and second pixel circuits located in the second row. Each of the first pixel circuits drives a first light emitting element, located in a column the same as a column in which the each of the first pixel circuits is located, among the first light emitting elements. At least one second pixel circuit of the second pixel circuits drives a second light emitting element, located in a column different from a column in which the at least one second pixel circuit is located, among the second light emitting elements.

Display panel, display driver and display device

A driving controller of a display device controls a scan driving circuit to sequentially drive a first group of scan lines among a plurality of scan lines to an active level during a first low-frequency frame when the operation mode is a low frequency mode and to sequentially drive a second group of scan lines among the plurality of scan lines to the active level during a second low-frequency frame, outputs an image data signal according to a first arrangement order of a plurality of color pixels in a first row during the first low-frequency frame, and outputs the image data signal according to a second arrangement order of the plurality of color pixels in a second row during the second low-frequency frame.

A display device includes a display panel including a plurality of pixel rows, and a panel driver which drives the display panel. The panel driver determines whether input image data represents a still image. When the input image data represents the still image, the panel driver determines a flicker value of the still image, applies a compensation value corresponding to a carry shift interval to the flicker value, determines a driving frequency for the display panel based on the flicker value to which the compensation value is applied, and performs an alternate driving operation for the display panel at the driving frequency.

Display device and method of operating the display device

A scan driver includes a control unit, a first output unit, a second output unit, and a masking control unit. The control unit outputs a first control signal to a first control node and outputs a second control signal to a second control node. The first output unit is connected to the first control node, a first output terminal, and a first voltage terminal, and operates in response to the first control signal. The second output unit is connected to the second control node, the first output terminal, and a second voltage terminal, and operates in response to the second control signal. The masking control unit is connected between an input terminal, to which a clock signal is input, and the first control node and controls a voltage level of the first control signal in response to a masking enable signal.

Scan driver including a first masking control unit and display device having the same

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Suwon-si, South Korea

Jaekeun Lim