Samsung Electronics Co., Ltd.

Jaejung Park

Myeongjin Oh

Haneul Jung

Sukho Shin

Hyosang Kim

Kyuik Cho

A digital-to-analog converter includes a first channel configured to output a first ramp voltage through an output node, and a first bias circuit configured to apply a bias voltage to the first channel. The first channel comprises a plurality of current cells connected to the first bias circuit, a plurality of selection circuits and a plurality of switches, and a first resistor connected to the output node. Each of the plurality of selection circuits of the first channel comprises a first selection circuit configured to connect a current of one of the plurality of current cells to the first resistor in accordance with a first digital input signal, and a second selection circuit configured to connect the current of the current cell to one of the plurality of switches corresponding to the current cell in accordance with a second digital input signal complementary to the first digital input signal.

Digital-to-analog signal converter and image sensor including the same

In an example embodiment, a ramp generator includes a ramp circuit that receives a first ramp enable signal from a control circuit during a first ramp period, the first ramp period including a first reset period and a first sensing period, and the ramp circuit being configured to output a first ramp signal to a correlated double sampling circuit; an emphasis circuit that increases a voltage level of the first ramp signal during the first reset period, based on a first enable signal received from the control circuit; and a pre-emphasis circuit that further increases the voltage level of the first ramp signal during a first pre-emphasis period in the first reset period, based on a second enable signal received from the control circuit.

Ramp generator including emphasis circuit and pre-emphasis circuit, operation method thereof, and image sensor device including the ramp generator

A driver circuit of an image sensor is provided. The driver circuit includes a row decoder to decode an address of a target row of a pixel array and generate an operation directing signal corresponding to the target row; a digital logic circuit including: a target row logic circuit to generate a pixel control signal based on the operation directing signal; a power switch configured to connect a power supply voltage to the target row logic circuit during a first time and isolate the power supply voltage from the target row logic circuit during a second time, based on the operation directing signal; and an output circuit configured to output a default signal during the second time; and a row driver configured to drive the target row based on the pixel control signal during the first time and drive the target row based on the default signal during the second time.

Growing community of inventors

Hwaseong-si, South Korea

Jaejung Park