Samsung Electronics Co., Ltd.

Jaejun Lee

Yong-jin Kim

Won-hyung Song

Jungjoon Lee

Kyoungsun Kim

Sangseok Kang

Jaesung Park

Kyudong Lee

Jinseong Yun

Yusung Joo

Wonshik Yoon

Bo-Ra Kim

Dongyeop Kim

Jeonghoon Baek

Woojin Na

Seonghoon Joo

Ilhan Choi

Minseong Im

Hyeseung Yu

Taegook Kim

Taegeun Yoo

Jinki Lee

Sukwon Jeong

Provided are an apparatus, a memory device, and a method for multi-phase clock training. The memory device includes a clock training circuit configured to receive a clock through a first signal pin, among a plurality of signal pins and connected to a first signal line connected to the first signal pin. The clock training circuit generates a multi-phase clock upon receiving the clock, and generates a three-dimensional (3-D) duty offset code (DOC) for the multi-phase clock by simultaneously phase-sweeping between three internal clock signals in a duty adjustment step in the multi-phase clock. The memory device corrects a duty error of the multi-phase clock using the 3-D DOC.

Apparatus, memory device, and method for multi-phase clock training

A semiconductor memory device includes a plurality of input-output pins configured to communicate with a memory controller, a command control logic, a temperature measurement circuit and an operation limit controller. The command control logic controls an operation of the semiconductor memory device based on command signals and control signals transferred from the memory controller through control pins among the plurality of input-output pins. The temperature measurement circuit measures an operation temperature of the semiconductor memory device to generate a temperature code corresponding to the operation temperature. The operation limit controller, when it is determined based on the temperature code that the operation temperature exceeds a risk temperature, controls an internal operation of the semiconductor memory device regardless of the command signals and the control signals transferred from the memory controller to thereby decrease a power consumption of the semiconductor memory device.

Semiconductor memory device with operation limit controller

A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.

Power management integrated circuit for monitoring output voltage, memory module including power management integrated circuit and memory device, and operating method of memory module

According to various embodiments, an electronic device comprises a communication circuit, a processor, and a memory electrically connected to the processor, wherein the memory, when executed, can store commands for allowing the processor to: receive, from a first external electronic device, a first synchronization signal including first identification information through the communication circuit; synchronize the electronic device with the first external electronic device on the basis of at least a part of the information included in the first synchronization signal; receive, from a second external electronic device, a second synchronization signal including second identification information through the communication circuit; and control, on the basis of the second identification information and the first identification information, whether synchronization with second external electronic device occurs. Additional various embodiments are possible.

Electronic device for performing device-to-device communication and method therefor

An electronic device is provided. The electronic device includes a display, a communication circuit, a memory, and a processor. The processor is configured to receive first system information broadcast from a base station using the communication circuit, connect to a cell associated with the base station based on the first system information using the communication circuit, and trigger, based on a frequency band of the cell and radio resource information about the cell, a first event indicating that device-to-device communication is possible or a second event indicating that the device-to-device communication is impossible.

Electronic device supporting device to device communication and method thereof

A motor of the invention includes a stator having a slot wound with a coil and a circular shaped housing accommodating the stator, and a rotor disposed on an inner surface of the housing and spaced apart from the slot and having a plurality of permanent magnets having the same number as magnetic poles and having different magnetic polarities. Each of the plurality of permanent magnets has a length corresponding to a first angle according to the number of magnetic poles. The plurality of permanent magnets are spaced apart from each other at a third angle according to the first angle and a second angle corresponding to the number of magnetic poles. The first, second, third angles of the motor refer to a center point of the housing as an angle reference point. The motor of an embodiment may be a motor provided in a washing machine.

Motor and washing machine having the same

Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system

A memory module includes a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area, a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab, and an insulating layer between the surface layer and the reference plane layer.

Selectively recessed reference plane structure in module tab area of memory module and method for forming selectively recessed reference plane

A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.

Memory module and memory system

A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.

Growing community of inventors

Suwon-si, South Korea

Jaejun Lee