Samsung Electronics Co., Ltd.

Jaejong Han

Sunghyun Choi

Kyungin Choi

Yong-Suk Tak

Bonyoung Koo

Seong Hoon Jeong

Kongsoo Lee

Jinhye Bae

Yoongoo Kang

Ho-Kyun An

Sungun Kwon

A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

Method of manufacturing semiconductor device using plasma doping process and semiconductor device manufactured by the method

Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Semiconductor memory devices having lower and upper interconnections, selection components and memory components

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Seoul, South Korea

Jaejong Han