Skc Solmics Co., Ltd.

Sk Enpulse Co., Ltd.

Skc Co., Ltd.

Enpulse Co., Ltd.

Jaein Ahn

Jang Won Seo

Sunghoon Yun

Jong Wook Yun

Hye Young Heo

Su Young Moon

Myung-Ok Kyun

Kyung Hwan Kim

Joonsung Ryou

Tae Kyoung Kwon

Hyeyoung Heo

A polishing pad includes a polyurethane, wherein the polyurethane includes in its main chain a silane repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is about 40 or less

Polishing pad, method for manufacturing polishing pad, and polishing method applying polishing pad

The present invention provides a polishing pad, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad, the surface zeta potential and its ratio of the polishing surface are controlled to specific ranges according to the type of polishing slurry, whereby it is possible to improve the characteristics of scratches and surface defects appearing on the surface of the semiconductor substrate and to further enhance the polishing rate.

Polishing pad and method for preparing semiconductor device using the same

Embodiments relate to a polishing pad, which comprises a window having a hardness similar to that of its polishing layer. Since the polishing pad comprises a window having a hardness and a polishing rate similar to those of its polishing layer, it can produce an effect of preventing scratches on a wafer during a CMP process. In addition, the polishing layer and the window of the polishing pad have a similar rate of change in hardness with respect to temperature, so that they can maintain a similar hardness despite a change in temperature during the CMP process.

Polishing pad comprising window similar in hardness to polishing layer

Embodiments relate to a porous polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polishing pad can be adjusted in light of the volume thereof. Thus, the plurality of pores have an apparent volume-weighted average pore diameter in a specific range, thereby providing a porous polishing pad that is excellent in such physical properties as polishing rate and the like.

Porous polishing pad and process for producing the same all fees

Embodiments relate to a porous polyurethane polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors and a process for preparing the same. According to the embodiments, the size and distribution of the plurality of pores contained in the porous polyurethane polishing pad can be adjusted. Thus, it is possible to provide a porous polyurethane polishing pad that has enhanced physical properties such as a proper level of withstand voltage, excellent polishing performance (i.e., polishing rate), and the like.

Porous polyurethane polishing pad and process for producing the same

A polishing pad includes a polyurethane, wherein the polyurethane includes a fluorinated repeating unit represented by Formula 1, wherein the number of defects on a substrate after polishing with the polishing pad and a fumed silica slurry is 40 or less; 

An embodiment relates to a polishing pad which is used in a chemical mechanical planarization (CMP) process and has excellent airtightness, wherein the polishing pad is excellent in airtightness of a window opening and thus can prevent water leakage that may occur during a CMP process.

Polishing pad having excellent airtightness

Provided is a polishing pad that comprises a plurality of first grooves that have a shape of geometric figures that share a center; and a plurality of second grooves that radially extend from the center to the outer perimeter, wherein the depth of the second grooves is equal to, or deeper than, the depth of the first grooves. It is possible for the polishing pad to rapidly discharge any debris generated during the polishing process to reduce such defects as scratches on the surface of a wafer.

Polishing pad with improved fluidity of slurry and process for preparing same

Embodiments relate to a leakage-proof polishing pad for use in a chemical mechanical planarization (CMP) process and a process for producing the same.

Leakage-proof polishing pad and process for preparing the same

The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.

Polishing pad that minimizes occurrence of defects and process for preparing the same

The embodiments relate to a porous polyurethane polishing pad and a process for preparing a semiconductor device by using the same. The porous polyurethane polishing pad comprises a urethane-based prepolymer and a curing agent, and has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 &#x3bc;m, a specific gravity of 0.7 to 0.9 g/cm, a surface hardness at 25&#xb0; C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm, an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 101 to 250 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 &#x3bc;m.

Porous polyurethane polishing pad and process for preparing a semiconductor device by using the same

The embodiments relate to a porous polyurethane polishing pad and a process for preparing a semiconductor device by using the same. The porous polyurethane polishing pad comprises a urethane-based prepolymer and a curing agent, and has a thickness of 1.5 to 2.5 mm, a number of pores whose average diameter is 10 to 60 &#x3bc;m, a specific gravity of 0.7 to 0.9 g/cm, a surface hardness at 25&#xb0; C. of 45 to 65 Shore D, a tensile strength of 15 to 25 N/mm, an elongation of 80 to 250%, an AFM (atomic force microscope) elastic modulus of 30 to 100 MPa measured from a polishing surface in direct contact with an object to be polished to a predetermined depth wherein the predetermined depth is 1 to 10 &#x3bc;m.

Growing community of inventors

Gyeonggi-do, South Korea

Jaein Ahn