Micron Technology Incorporated

Jaeil Kim

Suryanarayana B Tatapudi

John David Porter

Mijo Kim

Hao Ge

Methods, systems, and devices for auto-calibration of error detection signals are described. An error may be injected into a data signal obtained from a memory array. After injecting the error into the data signal, the data signal may be applied to an error detection circuit of the memory array, where the error detection circuit may output an error signal for the data signal. The error signal may be delayed relative to a control signal by a first amount. A timing signal that controls the propagation of the error signal may be obtained based on delaying the control signal by a second amount. Based on a comparison of the error signal and the timing signal, a third amount for delaying the control signal may be determined.

Auto-calibration of error detection signals

A system includes memory having a bank area and a channel area. The system further includes control circuitry to receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide a bank strobe signal for accessing memory in the bank area and at least two channel strobe signals for accessing memory in the channel area. The channel strobe signal may process a smaller amount of data than that processed by the bank strobe signal.

Read control signal generation for memory

Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Configurable link interfaces for a memory device

Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

Timing signal calibration for a memory device

A memory device may support multiple DQ maps. Two or more of the DQ maps may support memory operations using a same input-output width. In some examples, one or more components for supporting a DQ map for a different input-output width may be used to also support one or more of the DQ maps for the same-input output width.

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Boise, ID, United States of America

Jaeil Kim