Skhynix Inc.

Samsung Display Co., Ltd.

Jaeil Kim

Kihun Kwon

Yong Mi Kim

Ilyoung Jeong

Chang Hyun Kim

Gyoowan Han

Jae In Lee

Sang Hyun Ku

Soobum Park

Kuhyun Kang

BongSung Seo

Cheong-Wan Min

Daesuk Kim

Seokhwan Kim

Sanghyun Jung

Jongkil Han

Haksong Kim

Woodong Kim

Jeamin Lee

Seunghwan Jung

An apparatus for laser machining is provided including a stage for supporting a substrate and a controller for generating an error compensation table, a motor driver for moving the stage, and an error compensation unit for generating a table to compensate for an error. The error compensation unit includes a grid plate disposed on the stage and an imaging unit for imaging the grid plate. The motor driver outputs a position synchronization signal to the imaging unit according to a position of the stage. The imaging unit receives the position synchronization signal from the motor driver and images the grid plate while moving the stage.

Apparatus for laser machining and a method for compensating for errors of the same

A laser cutting apparatus and a laser cutting method are provided. A laser cutting method includes: preparing an object on a stage; cutting the object into a set shape by relatively moving and irradiating a laser beam along the set shape with respect to the object; and performing uniform heating compensation to reduce accumulation of thermal energy of the laser beam resulting from a change of speed at a shift point where a travelling direction of the laser beam with respect to the object changes.

Laser cutting apparatus and laser cutting method using the same

A semiconductor device includes an error count signal generation circuit and a row error control circuit. The error count signal generation circuit generates an error count signal which is enabled if the number of erroneous data of cells selected to perform an error scrub operation is equal to a predetermined number. The row error control circuit stores information concerning the number of the erroneous data in response to the error count signal if the number of the erroneous data is greater than or equal to the predetermined number or stores information concerning the number of row paths exhibiting the erroneous data in response to the error count signal after more erroneous data than the predetermined number is detected.

Semiconductor devices

A semiconductor device includes an initial buffer signal generation circuit and a buffer signal generation circuit. The initial buffer signal generation circuit includes an initial buffer circuit which is activated if an initialization operation terminates. The initial buffer signal generation circuit generates an initial buffer signal from an external control signal in response to a first reference voltage signal. The buffer signal generation circuit includes a buffer circuit which is activated in response to the initial buffer signal. The buffer signal generation circuit generates a buffer signal from the external control signal in response to a second reference voltage signal.

A semiconductor device includes an operation control circuit and a mode register activation signal generation circuit. The operation control circuit generates a chip identification storage control signal, a selection identification storage control signal, and a mode register set signal in response to an external set signal and a command. The mode register activation signal generation circuit generates a chip identification and a selection identification in response to the chip identification storage control signal and the selection identification storage control signal. The mode register activation signal generation circuit also generates a mode register activation signal for controlling a mode register set operation in response to the mode register set signal when the chip identification is identical to the selection identification.

Semiconductor devices and semiconductor systems including the same

A semiconductor device may include a multipurpose command latch circuit, a latched control signal generation circuit, and a training control circuit. The multipurpose command latch circuit may be configured to synchronize a multipurpose command with a first division clock signal to generate a first latched multipurpose command. The latched control signal generation circuit may be configured to latch a control signal in synchronization with the first division clock signal to generate a first latched control signal. The training control circuit may be configured to generate a training signal for executing a training operation of a chip selection signal from a first latched multipurpose command and a first latched control signal based on a training flag.

A semiconductor device may include a data input and output circuit (I/O) configured to selectively or simultaneously drive input and output lines according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.

Semiconductor memory device with burst mode

A semiconductor system includes a semiconductor device. The semiconductor device outputs a first group of data and a second group of data to a first group of input/output (I/O) lines and a second group of I/O lines in response to a command and an address. The second semiconductor device sequentially latches the first group of data loaded on the first group of I/O lines and the second group of data loaded on the second group of I/O lines to generate an output data or simultaneously latches the first and second groups of data loaded on the first and second groups of I/O lines to generate the output data, in response to a burst length information signal.

A semiconductor device includes a latch circuit and a first command generation circuit. The latch circuit generates a first internal control signal and a first internal chip selection signal in synchronization with an internal clock signal. The first command generation circuit generates a first normal command if the first internal chip selection signal having an enabled state is inputted in synchronization with an inverted internal clock signal. The first command generation circuit also generates a first control command if the first internal control signal having a second predetermined state is inputted in synchronization with the inverted internal clock signal.

A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.

An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a chip section signal and command/address signals. The second semiconductor device may be configured to enter a power-down operation based on the chip section signal and the command/address signals. The second semiconductor device may be configured to interrupt input of a first group of the command/address signals during the power-down operation. The second semiconductor device may be configured to selectively perform an on-die termination (ODT) operation according to a level combination of a second group of the command/address signals.

Semiconductor devices and integrated circuits including the same

A semiconductor device includes a control signal generation circuit and an input/output (I/O) control circuit. The control signal generation circuit generates first and second read control signals and first and second write control signals. One of the first and second read control signals and one of the first and second write control signals is selectively enabled according to a combination of first and second addresses for selecting a first I/O line or a second I/O line. The I/O control circuit outputs read data loaded on first and second internal I/O lines through any one of the first and second I/O lines in response to the first and second read control signals. In addition, the I/O control circuit outputs input data through any one of the first and second I/O lines in response to the first and second write control signals.

A method of aligning an alignment layer of a liquid crystal display (LCD) includes positioning a substrate on a stage; the substrate having the alignment layer provided thereon and the alignment layer including a plurality of alignment regions. Data identifying positions of the alignment regions relative to the alignment layer are loaded. A control signal for controlling a supply of light based on the loaded data identifying the positions of the alignment regions is generated. The light is supplied to the alignment regions according to the control signal and the alignment regions are aligned. The light is supplied from at least two different angles of incidence so that the alignment regions are aligned in at least two different directions.

Growing community of inventors

Yongin-si, South Korea

Jaeil Kim