Samsung Electronics Co., Ltd.

Jaeick Son

Sunghoon Kim

Changhun Kim

Moo-Kyung Lee

A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.

Non-volatile memory device

An integrated circuit of a semiconductor device is fabricated by forming patterns on a wafer in conformance with a layout of the patterns. A method for verifying the layout includes providing a virtual pattern on a predicted defect point in the layout, and identifying at least one pattern from among those of the layout using the virtual pattern. The predicted defect point corresponds to a weak point where it is determined in advance that a defect will occur when the layout is transcribed on a wafer. The identified pattern is a pattern that is adjacent to the virtual pattern in the layout.

Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same

A three-dimensional semiconductor device includes a semiconductor substrate including a cell array region and a peripheral circuit region, an electrode structure including electrodes vertically stacked on the cell array region, a MOS capacitor on the peripheral circuit region, an interlayer dielectric layer covering the electrode structure and the MOS capacitor, first and second power lines spaced apart from each other in a first direction and extending in a second direction on the interlayer dielectric layer, first lower plugs connected to the first power line and a first terminal of the MOS capacitor, and second lower plugs connected to the second power line to a second terminal of the MOS capacitor. The second power line is on one of the first lower plugs that is adjacent to some of the second lower plugs in one of the first and second directions.

Growing community of inventors

Hwaseong-si, South Korea

Jaeick Son