Electronics and Telecommunications Research Institute

Samsung Electronics Co., Ltd.

Jaehyun Kang

Cheon Soo Kim

Ja Yol Lee

Minjae Lee

Subin Kim

Junsu Jeon

Junsoo Ko

Byungmoo Kim

Minuk Heo

Joongwon Jeon

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Phase locked loop for reducing fractional spur noise

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Phase locked loop and operating method thereof

Growing community of inventors

Cheongju-si, South Korea

Jaehyun Kang