Samsung Electronics Co., Ltd.

Jaehyeoung Ma

Namhyun Lee

Geumjong Bae

Ho-jun Kim

Seungmin Song

Junggun You

Taeyong Kwon

Joohee Jung

Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.

Semiconductor devices

A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

Semiconductor device

A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

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Seongnam-si, South Korea

Jaehyeoung Ma