Samsung Electronics Co., Ltd.

Jaehun Jeong

Hansoo Kim

Sunil Shim

Jaehoon Jang

Donghyuk Chae

Youngho Lim

Jae-Hoon Jang

Sun-Il Shim

Kihyun Kim

Sunghoi Hur

Kyoung-Hoon Kim

Hoosung Cho

Su-Youn Yi

Wonseok Cho

Doogon Kim

Seung-hoon Baek

Hyeokchul Kwon

Haewoon Park

Yong-Hoon Son

Jinman Han

Jae-Joo Shim

Ju-Young Lim

Suyoun Lee

Seungjae Baik

Kihun Hwang

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Nonvolatile memory devices, operating methods thereof and memory systems including the same

Non-volatile memory devices, operating methods thereof and memory systems including the same

A touch display driving integrated circuit (IC) includes a touch driver IC and a source driver IC. The touch driver IC is to be connected to touch electrodes through touch sensing lines. The touch driver IC provides a sensing signal to first touch sensing lines among the touch sensing lines in a touch period, and applies a common voltage to the first touch sensing lines before the touch period is terminated. The source driver IC is to be connected to pixels through data lines.

Touch display driving integrated circuit, operation method of the same, and touch display device including the same

A touch display driving integrated circuit (IC) includes a touch driver IC configured to be connected to touch electrodes through touch sensing lines and provide a sensing signal to first touch sensing lines among the touch sensing lines in a touch period. The touch driver IC is further configured to apply a common voltage to second touch sensing lines among the touch sensing lines and apply a voltage different from the common voltage to third touch sensing lines different from the second touch sensing lines in a display period.

In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., NAND-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines.

Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors

Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region

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Hwaseong-si, South Korea

Jaehun Jeong