Samsung Electronics Co., Ltd.

Jaehue Shin

YongSung Cho

Insu Kim

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.

Memory device including page buffer circuit

A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

Growing community of inventors

Suwon-si, South Korea

Jaehue Shin