Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Jaehoon Shin

Daewon Kim

Beomjin Park

Kangmin Kim

Seungmin Song

Joongshik Shin

Geunwon Lim

Junggun You

Bongseok Suh

Hayong Jung

Wook Jae Lee

Jaeyun Lee

Sukhyung Park

Taeyoung Kim

Wook Su Lee

Seunghwan Lee

Jung-taek Kim

Yongjin Kwon

Sungil Park

Joonsuk Baik

Joohee Jung

Seokgyu Ban

Dongil Bae

Beyounghyun Koh

Sungsoo Ahn

Bongseob Yang

Dongwon Kim

Sung Hwan Kim

Keun Hwi Cho

Myung Gil Kang

Seokcheon Baek

Dongseog Eun

Kyeongjin Park

Myungkeun Lee

A semiconductor device including a substrate that includes first and second regions; a first active pattern on the first region and a second active pattern on the second region; a first gate electrode on the first active pattern and a second gate electrode on the second active pattern; and a first cutting pattern that penetrates the first gate electrode and a second cutting pattern that penetrates the second gate electrode, wherein a width of the first gate electrode as measured in one direction is less than a width of the second gate electrode, a maximum width of the first cutting pattern is greater than the width of the first gate electrode, and a minimum width of the second cutting pattern is less than the width of the second gate electrode.

Semiconductor device and method of fabricating the same

A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

Semiconductor devices including gate spacer

A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

Memory device

A sensing circuit of a display device includes a sensing line initialization circuit which substantially simultaneously initializes a first sensing line and a second sensing line in a first sub-sensing period of a sensing period, a first line selection switch which couples the first sensing line to a sensing channel in the first sub-sensing period, a second line selection switch which couples the second sensing line to the sensing channel in a second sub-sensing period of the sensing period, and the sensing channel which samples a first sensing voltage of the first sensing line in a first sampling period of the first sub-sensing period, and samples a second sensing voltage of the second sensing line in a second sampling period of the second sub-sensing period. The second sensing line is not initialized during a period from the first sampling period to the second sampling period.

Sensing circuit, display device and method of operating a sensing circuit

A sensing circuit includes a first line selection switch which connects a first sensing line to a sensing channel in a first sub-sensing period, a first noise selection switch which connects the first sensing line to a reference channel in a second sub-sensing period, a second line selection switch which connects a second sensing line to the sensing channel in the second sub-sensing period, and a second noise selection switch which connects the second sensing line to the reference channel in the first sub-sensing period. The sensing channel samples a first sensing voltage and noise of the first sensing line and the reference channel samples noise of the second sensing line in a first sampling period, and the sensing channel samples a second sensing voltage and noise of the second sensing line and the reference channel samples noise of the first sensing line in a second sampling period.

Sensing circuit, display device including sensing circuit, and method of driving sensing circuit

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

Integrated circuit devices having highly integrated NMOS and PMOS transistors therein and methods of fabricating the same

A display apparatus includes a display panel, a compensator, a controller, and a data driver. The compensator determines a degradation grayscale of a compensation region of the display panel. The degradation grayscale may be determined based on a driving time of at least one pixel in the compensation region and degradation data corresponding to the at least one pixel. The controller generates compensated image data for input image data based on the degradation grayscale. The data driver provides a data voltage to the at least one pixel based on the compensated image data.

Display apparatus and method of driving display apparatus

A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.

Semiconductor devices and data storage systems including the same

A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

Vertical memory devices

A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

Semiconductor device

Disclosed is a three-dimensional semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, first to fourth stack structures spaced apart in a first direction on the second substrate, first and second support connectors between the second and third stack structures, third and fourth support connectors between the third and fourth stack structures, and a through dielectric pattern penetrating the first stack structure and the second substrate. A first distance between the first and second support connectors is different from a second distance between the third and fourth support connectors.

Three-dimensional semiconductor memory devices

Growing community of inventors

Suwon-si, South Korea

Jaehoon Shin