Samsung Electronics Co., Ltd.

Jaehoon Lee

Seunghyun Oh

Jiyoung Kim

Younghun Seong

Jihye Kim

Wan Ho Kim

Seungjin Kim

Wanjae Ju

Bongtae Park

Yong Gyu Lim

Barosaim Sung

Yong Bin Lim

Taikuin Mun

Jaejoo Shim

Jaehyeok Lee

Minsoo Lee

Jaehong Jung

Satoru Yamada

Yong Kyun Lim

Bumhee Bae

Jaewon Park

Chanho Park

Namhyung Kim

Seunguk Han

Namho Jeon

Jeongnam Cheon

Jin-Seong Lee

Sangbong Lee

Byungki Han

Jun-Su Kim

Joomyoung Kim

Kiyul Lim

Hansu Pae

Jongkeun Choi

NamYoung Lee

Hyungi Seok

Taekon Kim

Wonjung Lee

Yelim Youn

Gihyeok Ha

Jinhyeon Lee

Sangkil Park

Sungjae Moon

Electronic devices are disclosed herein. Each device includes a display, communication circuitry and a processor. For each device, the respective processor executes registering a geographic locale indicator for the electronic device via a universally unique identified (UUID), equipment identity register (EIR) or manufacturer information. For a first device, a setup mode is executed, including transmitting the UUID, EIR, or manufacturer information to a second device, which may then determine is communication is possible with the first device based on the geographic locale indicator. The first device may receive a response indicative of whether the locales between the devices match. Based on the same, the first and/or second device may also display an indication as to whether communication is possible with the second device.

Electronic device and method for connecting the same to external device thereof

A flexible printed circuit board (FPCB) assembly includes an electrically conductive layer configured to transmit a signal, a dielectric layer provided on the electrically conductive layer, a ground layer provided on the dielectric layer, and an auxiliary metal layer provided on or under the ground layer, and connecting a plurality of regions of the ground layer to each other, where the electrically conductive layer, the dielectric layer, the ground layer, and the auxiliary metal layer are flexible.

Flexible printed circuit board assembly and electronic device including the same

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

Low dropout regulator providing variable offset and analog to digital conversion circuit including the same

A foldable electronic device is provided. The foldable electronic device includes a foldable housing including a first housing portion, a second housing portion, and a hinge structure connected with the first housing portion and the second housing portion, the foldable housing configured to be folded about a folding axis; a flexible display accommodated in the first housing portion and the second housing portion; a plurality of rigid printed circuit boards (RPCBs) including a first RPCB accommodated in the first housing portion and a second RPCB accommodated in the second housing portion; a first flexible printed circuit board (FPCB) configured to electronically connect with the first RPCB and the second RPCB, the first FPCB including a first flexible portion located through a designated area of the hinge structure, the first FPCB including a first rigid portion and a second rigid portion affixed to a part of the hinge structure; a second FPCB configured to electronically connect with the first RPCB and the second RPCB, the second FPCB including a second flexible portion located through the designated area of the hinge structure, the second FPCB including a third rigid portion and a fourth rigid portion affixed to a part of the hinge structure, wherein the second flexible portion of the second FPCB is spaced apart and substantially parallel from the first flexible portion of the first FPCB; and a bending-guide member attached to the first FPCB between the first rigid portion and the second rigid portion, and attached to the second FPCB between the third rigid portion and the fourth rigid portion such that the first flexible portion and the second flexible portion are held together.

Foldable electronic device

An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.

Analog-to-digital converting circuit receiving reference voltage from alternatively switched reference voltage generators and reference voltage capacitors and operating method thereof

A method of testing a memory device, a memory built-in self-test (MBIST) circuit, and a memory device for improving reliability and reducing a test time. The memory device includes a plurality of memory banks and the MBIST circuit. The MBIST circuit is configured to generate double data rate (DDR) test patterns and parallel bit test (PBT) test patterns to test the memory banks. When a defective cell is detected as a result of the PBT test or the DDR test, the MBIST circuit is configured to perform a repair operation for replacing the defective cell with a redundancy cell and perform a re-test to verify the repair operation. The MBIST circuit may be configured to perform the DDR test on one or more memory cells including the defective cell during the re-test.

Method of testing memory device, memory built-in self test (MBIST) circuit, and memory device for reducing test time

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

Clock integrated circuit including heterogeneous oscillators and apparatus including the clock integrated circuit

An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.

Split inverter, capacitor digital-to-analog converter and analog-to-digital converter of successive approximation register type including same

A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

Semiconductor device

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Comparator providing offset calibration and integrated circuit including comparator

An electronic device provided. The electronic device comprises at least one communication circuit configured to perform communication with at least one external device, at least one processor operatively connected with the at least one communication circuit, and a memory operatively connected with the at least one processor, wherein the memory stores instructions to, when executed, enable the at least one processor to control the at least one communication circuit to establish a first communication connection with a first wearable device, control the at least one communication circuit to receive a signal for establishing a second communication connection from a second wearable device, the signal including information indicating whether a user wears the second wearable device, identify whether the user wears the second wearable device based on the information, and based on identifying that the user wears the second wearable device, control the at least one communication circuit to release the first communication connection and establish the second communication connection with the second wearable device. Other various embodiments are possible as well.

Electronic device for establishing communication with external electronic device and method of controlling the same

A foldable electronic device is provided. The foldable electronic device includes a hinge structure, a foldable housing, a flexible display disposed inside the foldable housing, a first flexible connection member, a second flexible connection member, an adhesive member attached to the first flexible connection member. The foldable housing includes a first housing structure and a second housing structure. The first housing structure includes a first surface, a second surface, and a first printed circuit board. The second housing structure includes a third surface, a fourth surface, and a second printed circuit board.

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

Electronic device including equalizing circuit and operating method of the electronic device

Growing community of inventors

Suwon-si, South Korea

Jaehoon Lee