Samsung Electronics Co., Ltd.

Seoul National University

Gwanak Analog Co., Ltd.

Jaehoon Jun

Suhwan Kim

Han Vit Yang

Minsung Kim

Woong Joo

Youngwoo Lee

Cyuyeol Rhee

Beomsu Yun

Hyukbin Kwon

A circuit includes a first amplifier that first compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, second compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal in the first and second operation periods based on first and second comparison results; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, stops an operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts, and generates a second output signal based on the first output signal in the first operation period and the second operation period.

Analog-to-digital converting circuit using auto-zero period optimization and operation method thereof

Disclosed is an amplifier circuit including a first input terminal that receives a ramp signal, a second input terminal that receives a pixel signal, an output terminal that outputs an output signal, wherein the output signal is based on comparing the pixel signal and the ramp signal, a capacitor that is electrically connected between the output terminal and a ground terminal, a switch that is electrically connected with the capacitor, and a current source that outputs a power current. The pixel signal corresponds to a first conversion gain or a second conversion gain, and a value of the second conversion gain is higher than a value of the first conversion gain, and a bandwidth of the amplifier circuit is adjusted depending on whether the pixel signal corresponds to the first conversion gain or the second conversion gain.

Analog-to-digital converting circuits for dual conversion gain operation and operation methods of the same

In some embodiments, a circuit includes a first amplifier, a second amplifier, and a counter. The first amplifier operates based on a first power supply voltage and generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array during a first operation period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array during a second operation period. The second amplifier operates based on the first power supply voltage, generates a second output signal based on the first output signal and adjust a voltage level of the second output signal from a low level to a third level. The counter operates based on a second power supply voltage, counts pulses of the second output signal, and outputs a counting result as a digital signal.

Analog-to-digital converting circuit using output voltage clipping and operation method thereof

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal and generates a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal, and a second amplifier that generates a third output signal based on the first output signal and generates a fourth output signal based on the second output signal, the first conversion gain is higher than the second conversion gain, and a first power current of the first amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the first amplifier when the second pixel signal and the second ramp signal are compared.

Analog-to-digital converting circuit for optimizing dual conversion gain operation and operation method thereof

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

Analog-to-digital converting circuit for optimizing power consumption of dual conversion gain operation, operation method thereof, and image sensor including the same

An image sensor including: a pixel array including first and second pixels connected to a column line; a row driver to provide the first pixel with a first selection signal based on a clamp voltage, and to provide the second pixel with a second selection signal based on a selection voltage, wherein the first pixel outputs a first output voltage in response to the first selection signal, and the second pixel outputs a second output voltage in response to the second selection signal, wherein the first and second output voltages are output as a pixel signal through the column line, wherein a voltage of the pixel signal corresponds to a voltage obtained by clamping the second output voltage with the first output voltage, and wherein a change in a voltage level of the first output voltage due to a temperature is compensated for by the clamp voltage.

Electronic circuit for compensating a voltage level against a variation of temperature, and an image sensor including the same

An image sensor supporting a full resolution mode and a crop mode, the image sensor including: a pixel array including a plurality of pixels configured to generate a pixel signal by sensing an object; an analog-to-digital converter configured to convert the pixel signal into a digital signal and including a plurality of metal lines; a bias generator configured to apply a bias voltage to the plurality of metal lines; and a bias controller including: a first transistor configured to activate all of the plurality of metal lines based on a first control signal; and a second transistor configured to activate a first metal line for the crop mode among the plurality of metal lines based on a second control signal.

Analog-to-digital converter for separately applying a bias voltage depending on an operation mode, and an image sensor including the same

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

Analog-to-digital converting circuit using output signal feedback and operation method thereof

A delta-sigma modulator generates a bit stream signal from an analog signal by operating according to a modulation period including a sampling period and a filtering period and includes a digital-to-analog converter (DAC) configured to generate a charge signal according to one of a first reference voltage and a second reference voltage according to the bit stream signal during the sampling period and to output a signal generated according to the charge signal and the other of the first reference voltage and the second reference voltage; a loop filter configured to charge a sampling signal corresponding to the analog signal during the sampling period and to filter an output from the DAC and a signal generated according to the sampling signal during the filtering period; and a quantizer configured to generate the bit stream signal according to an output from the loop filter in the modulation period.

Delta-sigma modulator and analog-to-digital converter including the same

An analog-to-digital converter (ADC) includes an input circuit configured to receive a first analog signal output from a first sensor or a second analog signal output from a second sensor according to an operation mode and a bit stream; a filter configured to filter an output signal from the input circuit; a quantization circuit configured to generate the bit stream from an output signal of the filter; and a digital circuit configured to generate a first digital signal corresponding to the first analog signal or a second digital signal corresponding to the second analog signal by filtering the bit stream, wherein the operation mode includes a first mode selecting the first sensor and a second mode selecting the second sensor, and wherein the digital circuit refers to the second digital signal generated during the second mode to generate the first digital signal during the first mode.

Analog-to-digital converter for converting analog signals input from a plurality of sensors

A semiconductor device includes a signal input circuit configured to select one of the plurality of differential sensor signals according to a channel selection signal; an amplifier circuit configured to amplify an output of the signal input circuit; and an analog-to-digital converter (ADC) configured to convert an output of the amplifier circuit into a digital value, wherein each of the plurality of sensor signals is a differential signals and the signal input circuit changes polarity of an output signal thereof according to a first chopping signal, and wherein the ADC includes a delta-sigma modulator configured to generate a bit stream from an output of the amplifier circuit; an output chopping circuit configured to adjust phase of the bit stream according to the first chopping signal; and a filter configured to filter an output of the output chopping circuit and to output the digital value.

Growing community of inventors

Seoul, South Korea

Jaehoon Jun