Samsung Electronics Co., Ltd.

Jaeho Shin

Jeongho Lee

Younggeon Yoo

Insu Jeon

Hyeokjun Choe

Hyeokshin Kwon

Jaehyeong Lee

Taehwan Jang

Wonseb Jeong

Younho Jeon

Ipoom Jeong

Hyodeok Shin

Sangoak Woo

Youngkwang Yoo

Kwangjin Lee

Hee Hyun Nam

Heehyun Nam

JeongHo Lee

Jinhyoun Kang

Sungho Han

Hyun Jae Oh

A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

Superconducting qubit memory of quantum computer

An active circulator includes: an active filter; and a power divider serially connected to the active filter, wherein three or more combinations of the active filter and the power divider are connected to form a loop.

Active circulator and quantum computer system with active circulator

An electronic device includes an input handling circuit, a control circuit, and a data transfer circuit. The input handling circuits receives a first request including an address from a first memory device, aligns the address with an access unit of a second memory device, requests a determination for the aligned address, and transmits a second request to the second memory device based on a determination result. The control circuit determines, based on the request, whether a duplicate address with the aligned address is present to generate the determination result and updates a bitmask based on the determination result. The data transfer circuit receives the second request from the second memory device and transfers data based on the bitmask. The bitmask includes one or more bits, each corresponding to the first request and indicating a location corresponding to the first request within an access unit of the second memory device.

Electronic device managing duplicate requests and method of operating the same

In a method of allocating and protecting a memory in a computational storage device including a first computing engine and a buffer memory, a memory allocation request is received from a host device that is disposed outside the computational storage device. Based on the memory allocation request, a memory allocation operation in which a first memory region is generated in the buffer memory and a first key associated with the first memory region is generated is performed. A program execution request is received from the host device. Based on the program execution request, a program execution operation is performed in which a first program is executed by the first computing engine by accessing the first memory region based on an encryption or a decryption using the first key.

Method of allocating and protecting memory in computational storage device, computational storage device performing the same and method of operating storage system using the same

A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

System, device and method for accessing device-attached memory

Disclosed is a method of performing, at a controller, an access to a memory device, which includes transmitting, at the controller, a first command signal, a first address signal, and a first swizzling signal to the memory device, selecting first data bits stored in a memory cell array of the memory device based on the first command signal and the first address signal, and sequentially outputting, at the memory device, at least a part of the first data bits to the controller in a burst manner, based on the first swizzling signal.

Semiconductor memory device and operation method of swizzling data

Growing community of inventors

Gwangmyeong-si, South Korea

Jaeho Shin