Samsung Electronics Co., Ltd.

Jaeho Jeong

Sooyong Lee

Jeeyong Lee

Taehoon Kim

Jang-Gn Yun

Sunghoi Hur

Sunyoung Kim

Hoosung Cho

Jongwon Kim

Changwook Jeong

Jeonghoon Ko

Yejin Jeong

Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.

Method and computing device for manufacturing semiconductor device

A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

Proximity correction methods for semiconductor manufacturing processes

Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

Three-dimensional semiconductor devices having vertical structures of different lengths

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Suwon-si, South Korea

Jaeho Jeong