Rambus Inc.

Seoul National University

Silicon Image Gmbh

True Circuits, Inc.

Samsung Electronics Co., Ltd.

Skhynix Inc.

Leland Stanford Junior University

Korea Institute of Science and Technology

Snu Rdb Foundation

Jaeha Kim

Brian S Leibowitz

Hae-Chang Lee

Jared L Zerbe

Jafar Savoj

Jihong Ren

Seungheon Baek

Mark A Horowitz

Deog-Kyoon Jeong

Huy M Nguyen

Yohan Usthavia Frans

Qi Lin

Jung-Hoon Chun

John George Maneatis

Haechang Lee

Daniel Karl Hartman

Yunju Choi

Brent Steven Haukness

Youngjun Kim

Gyudong Kim

Hyun Soo Park

Craig Steven Levin

Min-Kyu Kim

Jong Hyun Shin

Thomas H Greer, Iii

Jung-Ik Ha

Jaeyoung Park

Seuk Son

Yonghwan Oh

Bong-Joon Lee

Kevin D Jones

Taewook Kang

Brian Liebowitz

Frances W Y Lau

Hwang Ho Choi

Won Jun Choe

Joonseok Yang

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Integrated circuit having receiver jitter tolerance ('JTOL') measurement

A neural array may include an array unit, a first processing unit, and a second processing unit. The array unit may include synaptic devices. The first processing unit may input a row input signal to the array unit, and receive a row output signal from the array unit. The second processing unit may input a column input signal to the array unit, and receive a column output signal from the array unit. The array unit may have a first array value and a second array value. When the first processing unit or the second processing unit receives an output signal based on the first array value from the array unit which has selected the first array value and then the array unit selects the second array value, it may input a signal generated based on the output signal to the array unit which has selected the second array value.

Neural array having multiple layers stacked therein for deep belief network and method for operating neural array

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Receiver with enhanced clock and data recovery

Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Decision feedback equalizer

A neuron device may include an input unit, a synapse unit, and an output unit. The synapse unit can be connected with the input unit and may include one or more synapse modules. Each of the one or more synapse modules may include multiple synapse elements connected in series and may be configured to operate in a time division multiplexing mode. Each synapse element may have specific coefficient information. In each of the one or more synapse modules, one of the multiple synapse elements connected in series may be configured to apply coefficient information to one of the multiple input signals received by the input unit. The output unit may obtain a weighted sum of the multiple input signals and may generate an output signal based on the weighted sum.

Neuron device and integrated circuit including neuron device

A circuit module includes a model circuit and a look-up table (LUT). The model circuit generates an output signal based on one or more input signals, and corresponds to a digital circuit. The LUT stores one or more control signals and one or more operation parameters that are to be used to implement the model circuit. The one or more control signals and the one or more operation parameters correspond to an index determined by a combination of the one or more input signals and the output signal.

Circuit module for modelling a digital circuit and simulation device including the circuit module

Apparatus and method for controllably injecting jitter into recovered clock to simulate presence of jitter in input signal

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

An apparatus for generating tactile stimulation includes vibration actuators disposed on opposing sides of a finger, and a sensor configured to detect a position and a pointing direction of the finger, wherein the vibration actuators apply vibration to the finger with intensity and duration determined by the position and the pointing direction of the finger detected by the sensor, and wherein illusory stimulation is generated within the finger by the vibration generated by the vibration actuators.

Vibrating apparatus, system and method for generating tactile stimulation

A power supply and a gate driver includes a power switching element to control current, a control circuit to output a control signal for opening or closing of the power switching element, and a gate drive circuit to open or close the power switching element in accordance with the control signal. The gate drive circuit includes a first inductive circuit connected to a supply voltage source, and a second inductive circuit connected to an input stage of the power switching element, and transfers electrical energy stored in the input stage of the power switching element, using the first and second inductive circuits. Accordingly, electrical energy supplied to the input stage of the power switching element during an ON state of the power switching element is again recovered during an OFF state of the power switching element.

Power supply and gate driver therein

Growing community of inventors

Los Altos, CA, United States of America

Jaeha Kim