Samsung Electronics Co., Ltd.

Jaeha Eom

Younghun Han

Mooyoung Kim

Kwanghyun Lee

Seunghoon Jung

Sujong Jang

Inje Jeong

An image sensor includes an active pixel array, at least one dummy reset array, a dummy read array, and an image processor. The image processor sequentially resets respective rows of pixels included in the at least one dummy reset array in a period in which pixels of the active pixel array do not perform a reset operation, and sequentially reads respective rows of pixels included in the dummy read array in a period in which the pixels of the active pixel array do not perform a read operation.

Image sensor and method of operating the same with resetting of a dummy reset array and reading of a dummy read array

An image sensor includes an analog-to-digital conversion circuit that receives pixel signals from column lines, respectively, and converts the pixel signals into first pixel values, respectively. Data buffer clusters correspond to enable signals transferred from a timing controller, respectively, and output second pixel values. Each of the data buffer clusters stores first pixel values, which correspond to some column lines consecutively arranged among the column lines, among the first pixel values and output stored pixel values as some second pixel values among the second pixel values in response to a corresponding enable signal. A digital processing circuit performs digital processing on the second pixel values output from the data buffer clusters.

Image sensor with data buffer clusters

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

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Seoul, South Korea

Jaeha Eom