Samsung Electronics Co., Ltd.

Jaegeun Park

Youngjin Cho

Jinwoo Kim

Sangmuk Hwang

Hojun Shim

Youngkwang Yoo

Byungchul Yoo

Jongin Lee

Kui-Yon Mun

Soon Suk Hwang

Seonghoon Woo

Younggeun Lee

Hyo-Deok Shin

Kyuwook Han

Kwang Hee Choi

Hyunwoo Kang

Biwoong Chung

Haksun Kim

Euihyeok Kwon

Joonsung Bae

Seong Yeon Kim

Youngsuk Moon

An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

Address translation cache and system including the same

A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

Storage controller managing completion timing, and operating method thereof

A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

Memory controller and memory system

A method of operating a storage controller that communicates with a host including a submission queue and a completion queue is provided. The operating method includes receiving a submission queue doorbell from the host, fetching a first command including a latency from the submission queue of the host in response to the received submission queue doorbell, processing the fetched first command, and writing a first completion, which indicates that the first command is completely processed, into the completion queue of the host at a timing based on the latency.

A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

Nonvolatile memory capable of outputting data using wraparound scheme, computing system having the same, and read method thereof

A method for accessing a random-accessible nonvolatile RAM includes externally receiving a base address, receiving a relative address corresponding to an increasing or decreasing size from the base address, and reading data stored in a memory area of the nonvolatile RAM or writing externally provided data into the nonvolatile RAM with reference to the base address and the relative address.

Access methods of memory device using relative addressing

A dynamic random access memory (DRAM) device includes a memory cell array including a plurality of memory cells, a refresh controller configured to perform a plurality of refresh operations on the plurality of memory cells in response to a plurality of refresh commands from an external device, and a refresh counter configured to count a number of the refresh commands for a fixed period of time and compare the counted number with a threshold. The refresh counter is configured to generate a power failure signal to cause the DRAM device to enter a power failure mode in response to the comparison of the counted number with the threshold. The refresh controller is configured to perform a refresh operation on the plurality of memory cells without control of the external device in the power failure mode.

Dynamic random access memory device and operating method with improved reliability and reduced cost

A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.

Storage system managing run-time bad cells

A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Nonvolatile memory device and program method thereof

A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.

Memory controller and memory system including the same

Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.

Interface circuit operating to recover error of transmitted data

A delay locked loop (DLL) is provided. The DLL includes a delay line, a phase detector, a delay line control unit, and a DLL controller. The delay line outputs an output clock by delaying an input clock by a first time on the basis of a select value. The phase detector detects a phase of the output clock. The delay line control unit determines a select value so that the first time corresponds to n periods of the input clock on the basis of the detected phase and an initial select value. The DLL controller provides the initial select value to the delay line control unit. The DLL controller updates the initial select value according to a change of a frequency of the input clock, and to provide the updated initial select value to the delay line control unit.

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Suwon-si, South Korea

Jaegeun Park