Samsung Electronics Co., Ltd.

Jaeeun Lee

Yeongkwon Ko

Junyeong Heo

Teakhoon Lee

Jaekyung Yoo

Junseok Kim

Donghoon Won

Jayeon Lee

Hyunsook Yoon

Hyoseok Woo

There is provided a method of dicing a semiconductor wafer, which includes providing a semiconductor substrate having a plurality of integrated circuit regions on an active surface of the semiconductor substrate, a dicing regions provided between adjacent integrated circuit regions of the plurality of integrated circuit regions, and a metal shield layer provided on the active surface across at least a portion of the adjacent integrated circuit regions and the dicing region, forming a modified layer by irradiating laser to an inside of the semiconductor substrate along the dicing region, propagating a crack from the modified layer in a direction perpendicular to a major-axial direction of the metal shield layer by polishing an inactive surface opposing the active surface of the semiconductor substrate and forming semiconductor chips by separating the adjacent integrated circuit regions, respectively, based on the crack propagating from the modified layer.

Semiconductor substrate and method of dicing the same

A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

Semiconductor device and semiconductor package including the same

A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

Semiconductor package including part of underfill on portion of a molding material surrounding sides of logic chip and memory stack on interposer and method for manufacturing the same

A semiconductor device includes a first metal wiring pattern area, and a second metal wiring pattern area that does not overlap the first metal wiring pattern area in a plan view. The first metal wiring pattern area includes a first pattern, the second metal wiring pattern area includes a second pattern that is spaced apart from the first pattern and includes one or more lines. The first metal wiring pattern area includes an assist pattern comprising one or more lines. The assist pattern is spaced apart from the second pattern, parallel with the second pattern, and is between the first pattern and the second pattern. One end of the assist pattern is connected to the first pattern.

Semiconductor device including plurality of patterns

Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

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Suwon-si, South Korea

Jaeeun Lee