Samsung Electronics Co., Ltd.

Jaeduk Yu

Yonghyuk Choi

Bongsoon Lim

Yohan Lee

Sangwan Nam

Sangwon Park

Dongkyo Shim

Sangsoo Park

Jiho Cho

Daeseok Byeon

Jinyoung Kim

Hongsoo Jeon

Jonghoon Park

Chaehoon Kim

A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

Memory device and operating method thereof

A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.

Method of determining and preprogramming over-erases groups of memory cells

A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.

Memory device including string select transistors having different threshold voltages and method of operating the memory device

Provided is an operating method of a nonvolatile memory device. The operating method includes receiving a read command, increasing a voltage applied to a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period, applying a first voltage to a first selected ground selection line corresponding to a first process characteristic, until a first time in the word line setup period, applying a second voltage to the first selected ground selection line after the first time in the word line setup period, applying the first voltage to a second selected ground selection line corresponding to a second process characteristic, until a second time earlier than the first time in the word line setup period, and applying the second voltage to the second selected ground selection line after the second time in the word line setup period.

Nonvolatile memory device and operating method thereof

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.

Non-volatile memory device including multi-stack memory block and operating method thereof

A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

Nonvolatile memory device having multi-stack memory block and method of operating the same

A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.

Semiconductor device and massive data storage system including the same

Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

Non-volatile memory device

A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

Nonvolatile memory device and method of programming in a nonvolatile memory

Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.

Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods

A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

Memory system and method of operating the same

A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

Nonvolatile memory device having cell-over-periphery (COP) structure with address re-mapping

A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

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Seoul, South Korea

Jaeduk Yu