Skhynix Inc.

Hewlett Packard Enterprise Development LP

Toshiba Memory Corporation

Jae Yun Yi

Frederick A Perner

Tatsuya Kishi

Keiji Hosotani

Satoshi Inaba

Keisuke Nakatsuka

Hisanori Aikawa

Masaru Toko

Jinwon Park

Jae Yeon Lee

Se Dong Kim

Sung Won Chung

Seok Pyo Song

Sangmin Hwang

Kwangmyoung Rho

Hong Ju Suh

Jeong Hwan Kim

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Resistance change memory

In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Three dimensional resistive memory architectures

A nonvolatile memory apparatus includes: a memory cell coupled to a bit line and a source line; a word line configured to select the memory cell; and a local switch block configured to apply a write voltage, a read voltage, and a source line voltage to the bit line and the source line in response to a local switch select signal. In a write or read operation of the nonvolatile memory apparatus, the word line has a first voltage level, and the local switch select signal has a second voltage level higher than the first voltage level.

Nonvolatile memory apparatus for controlling a voltage level of enabling a local switch

Growing community of inventors

Icheon, South Korea

Jae Yun Yi