Samsung Electronics Co., Ltd.

Jae-Yun Lee

Kwang-Jin Lee

Beak-Hyung Cho

Dong-Hoon Jeong

Il Han Park

Byung Soo Kim

Sang-Soo Park

Jong-Hoon Lee

Woo-Jung Sun

Joon Soo Kwon

Jin-Young Kim

Il-Han Park

Kang-Bin Lee

Byung-Soo Kim

Jun-yong Park

Min-Gu Kang

Su-Yong Kim

Na-Young Choi

Sun Woo-Jung

A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Memory device including a circuit for detecting word line defect and operating method thereof

Provided is a nonvolatile memory device and an operating method thereof. The operating method for programming a first memory block from among a plurality of memory blocks includes: programming a first word line connected to the first memory block by sequentially executing first to N(N is a natural number) programming loops; applying a voltage generated by regulating a first pump voltage of a first charge pump to the first word line as a dummy verifying voltage after the programming is completed; generating a first detection count based on the first pump voltage and a first reference voltage; and outputting a bad block setting signal for setting the first memory block as a bad block based on a result of comparing the first detection count with the first reference count.

Nonvolatile memory device and operating method thereof

A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.

Memory devices including a word line defect detection circuit

Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.

Driving method of nonvolatile memory device using variable resistive element

Provided are nonvolatile memory devices and a driving method of the nonvolatile memory devices. The nonvolatile memory devices may include a plurality of memory banks, a read global bit line shared by the plurality of memory banks, a write global bit line shared by the plurality of memory banks, a read circuit connected with the read global bit line and performing a read operation, and a discharge control circuit connected with the write global bit line and primarily discharging the write global bit line during an initialization interval after a power-up operation.

Nonvolatile memory device with reduced coupling noise and driving method thereof

A nonvolatile memory device utilizes a variable resistive element. The nonvolatile memory device includes a plurality of banks and first to third write global bit lines arranged to cross the plurality of banks. Each of the plurality of banks includes a plurality of nonvolatile memory cells using resistive material. The first, the second and the third write global bit lines are disposed directly adjacent to one another in order. When a write current is supplied to the first write global bit line during a write period, a fixed voltage is applied to the second write global bit line while the third global bit line floats.

Nonvolatile memory device using variable resistive element

A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

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Anyang-si, South Korea

Jae-Yun Lee