Samsung Electronics Co., Ltd.

Sungkyunkwan University

Jae Youl Lee

Hyun Wook Lim

Tae Jin Kim

Dong Hoon Baek

Jin Ho Kim

Tae-Jin Kim

Sang Kyu Lee

Jong Hyuk Lee

Kwi Sung Yoo

Jung-Hoon Chun

Young Min Choi

Chang Hoon Baek

Se Whan Na

Hwa Hyun Cho

Eun Young Jin

Young Hwan Chang

Yong Hoon Yu

Ho Seok Shin

Yoon Ho Ko

Joo Hyuk Yum

Byoung Yoon Jang

Tae Kon Yu

Dong Myung Lee

Ji Heon Ok

Un Ki Park

Kyong Ho Kim

Woon Taek Oh

A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

Signal receiving device and method of recovering clock and calibration of the device

A degradation compensation device and an organic light emitting display device including the same are provided. The degradation compensation device includes a degradation rate acquisition unit acquiring estimated degradation rates, estimated with respect to a plurality of respective pixels, based on panel usage information, a digital compensation unit performing digital compensation to lower a digital gradation of each pixel, based on a luminance of a pixel having a maximum degradation rate, among the estimated degradation rates, and an analog compensation unit performing analog compensation to increase luminance of the plurality of pixels by changing an analog voltage supplied to a panel, after performing the digital compensation.

Degradation compensation device and organic light emitting display device including the same

A display driving device includes a timing controller configured to generate test data having a predetermined periodicity, and a source driver configured to drive source lines of a display panel using the test data, determine that a bit error has been generated when aperiodicity appears in the test data, and measure a bit error rate (BER) based on the bit error.

Display driving device

A display driver includes an interface circuit configured to receive an input image of a virtual reality (VR) experience from at least one of an application processor (AP) and a graphics processing unit (GPU); a coordinate correction circuit configured to generate corrected coordinates by adjusting input coordinates of pixels included in the input image; and an image generation circuit configured to generate an output image by distorting the input image using the corrected coordinates.

Display driver and mobile electronic device

An image processing apparatus includes: an analyzer configured to calculate color characteristics by input pixel data, and determine whether the pixel data is achromatic based on the color characteristics; a first renderer configured to perform a first rendering on the pixel data in response to determining that the pixel data is not achromatic; and a second renderer configured to perform a second rendering on the pixel data in response to determining that the pixel data is achromatic.

Image processing apparatus and method, and electronic device

A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

Display device

A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.

Phase locked loop for preventing harmonic lock, method of operating the same, and devices including the same

A clock data recovery circuit including: a digital phase detector and deserializer configured to sample serial data using a recovery clock signal to generate an up phase error signal and a down phase error signal which correspond to a phase difference between the serial data and the recovery clock signal; a digital loop filter configured to generate an up fine code and a down fine code based on a result of counting the up and down phase error signals; a loop combiner configured to generate an up fine tuning code and a down fine tuning code by using the up and down phase error signals and the up and down fine codes; and a digitally controlled oscillator configured to generate the recovery clock signal having a frequency changed with the up and down fine tuning codes.

Clock data recovery circuit and a method of operating the same

Growing community of inventors

Gyeonggi-do, South Korea

Jae Youl Lee