Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Skhynix Inc.

University of Michigan

Jae-Yoon Sim

Jei-Hwan Yoo

Jung-Bae Lee

Soo-In Cho

David Theodore Blaauw

Seung-Hoon Lee

Dennis Sylvester

Ho-young Kim

Hyong-Ryol Hwang

Jae-Youl Lee

Ki-Chul Chun

Dong-hoon Baek

Dong-Myung Lee

Massimo Alioto

Yoonmyung Lee

Young-hun Seo

Young-sang Kim

Hong-joon Park

Hong-Joon Park

Dong-bee Jang

Hyunwoo Son

Yen-po Chen

A neuromorphic system includes a first neuromorphic layer configured to perform a forward operation with an input signal and a first weight, a first operation circuit configured to perform a first operation on a result of the forward operation of the first neuromorphic layer, a second neuromorphic layer configured to perform a forward operation with an output signal of the first operation circuit and a second weight, a second operation circuit configured to perform a second operation on a result of the forward operation of the second neuromorphic layer, a first weight adjustment amount calculation circuit configured to calculate a first weight adjustment amount, and a second weight adjustment amount calculation circuit configured to calculate a second weight adjustment amount.

Neuromorphic system for performing supervised learning using error backpropagation

The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.

Display driving circuit

An electrostatic discharge clamp circuit is provided for low power applications. The clamp circuit includes: a detection circuit, a bias circuit and a shunting circuit having at least one shunt transistor. The detection circuit is configured to detect an occurrence of an electrostatic charge on a power supply node and trigger discharge of the electrostatic charge through the shunting circuit. The bias circuit is coupled between the detection circuit and the shunting circuit and applies a bias voltage to the gate terminal of the shunt transistor. During an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially equal to the supply voltage; whereas, during the absence of an electrostatic discharge event, the bias circuit is configured to generate a bias voltage that is substantially half of the supply voltage.

Electrostatic discharge clamp circuit for ultra-low power applications

A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Broadband multi-phase output delay locked loop circuit utilizing a delay matrix

A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Negative voltage generator for a semiconductor memory device

A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activating bitline equalizing circuits to precharge the bitlines of at least one of the first and second memory block with a bitline precharge voltage, when the memory block is not currently selected for a data operation. The bitline equalizing voltage generator may be configured to recycle the boost voltage that was used to generate a bitline isolation signal or a wordline drive signal.

Memory device that recycles a signal charge

A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.

Voltage boosting circuit and method of generating boosting voltage, capable of alleviating effects of high voltage stress

A semiconductor integrated circuit may include an internal circuit, and a power-on reset circuit for generating a power-on reset signal to initialize the internal circuit at a power-on. At the power-on, the power-on reset circuit delays a transition of the power-on reset signal from a first level to a second level until a given time duration after the power supply voltage reaches a detection voltage.

Power-on reset circuit, semiconductor integrated circuit device including the same and method for generating a power-on reset signal

A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

Semiconductor memory device with a decoupling capacitor

A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed. Therefore, according to the semiconductor device including the high frequency equalizer, the lost high frequency component of data can be restored even at a high data transmission speed.

High frequency equalizer using a demultiplexing technique and related semiconductor device

Disclosed is a semiconductor memory device which includes an offset-compensated amplifier circuit. The offset-compensated amplifier circuit enables a flip-flop sense amplifier to perform a stable sensing operation irrespective of its own offset voltage. A part of the offset-compensated amplifier circuit is located in a first region (for example, a region that includes the flip-flop sense amplifier), and the other thereof is located in a second region (for example, a region where drivers related to the flip-flop sense amplifier are located). With this distributed arrangement structure, an offset-compensated amplifier circuit can be obtained n the semiconductor memory device.

Semiconductor memory device with offset-compensated sensing scheme

A voltage booster circuit includes first and second capacitors and a switch circuit coupled to the first and second capacitors and operative to apply a power supply across the first and second capacitors in series responsive to a first signal to thereby charge the first and second capacitors and to couple the first and second capacitors in parallel between an output terminal and a power supply node of the power supply responsive to deassertion of the first signal and assertion of a second signal to thereby boost a voltage at the output terminal. The first and second signals may be alternately asserted in a succession of time periods, e.g., the first and second signals may be asserted in respective non-overlapping time periods.

Low-voltage booster circuits and methods of operation thereof

A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Negatively biased word line scheme for a semiconductor memory device

A semiconductor memory device includes a plurality of main word lines. A plurality of sub word lines correspond to each one of the main word lines. A plurality of sub word line drivers are also included, wherein each sub word line driver corresponds to one of the sub word lines and connects the corresponding sub word line to the corresponding main word line. The sub word line drivers charge the sub word lines up to a boosting voltage regardless of an activation order between a sub word line selection signal and the main word line. The sub word line drivers can include a first transistor for transferring the sub word line selection signal to the sub word line in response to an activation of the main word line. A second transistor is configured to connect the main word line to the sub word line in response to an activation of the sub word line selection signal. A third transistor is configured to connect the main word line to a gate of the first transistor in response to a high voltage. And a fourth transistor is configured to connect the sub word line selection signal to a gate of the second transistor in response to the high voltage.

Growing community of inventors

Kyunggi-do, South Korea

Jae-Yoon Sim