Postech Academy-industry Foundation

Samsung Electronics Co., Ltd.

Postech Research and Business Development Foundation

Skhynix Inc.

Jae Yoon Sim

Hyun Surk Ryu

Jun Seok Kim

Seon Kyoo Lee

Young Woo Ji

Jun Haeng Lee

Jun Hwi Choi

Jae Koo Lee

Hwa Suk Cho

Keun Woo Park

Yong Ju Kim

Hong June Park

Seung Hwan Hong

Chang Woo Shin

In Hwa Jung

Kyong Tai Kim

Kyoung Ho Lee

Hwasuk Cho

Min Seob Lee

Jong Mi Lee

Ki Seo Kang

Seungnam Choi

Ja Hyun Koo

Jae Han Park

Kyu Jin Choi

Dong Woo Jee

Kyung Chul Woo

Byung Jun Kim

Jun Seok Km

The present disclosure provides a cryptographic processor device capable of performing the post-quantum cryptographic encryption with in a high speed with low power, allowing a change of encryption parameters, and handling various cryptographic protocols. The cryptographic processor device executing polynomial vector operations required for a post-quantum cryptography includes: a polynomial memory bank configured to store a plurality of polynomial vectors; and an arithmetic and logic operator configured to perform operation on the polynomial vectors. The arithmetic and logic operator includes a transform operation circuit configured to multiply two polynomial vectors read out from the polynomial memory bank by using a predetermined transform operation including a plurality of operation stages, and including a combined operation unit configured to consecutively perform a first stage operation and a second stage operation among the plurality of operation stages without storing a result of the first operation stage in a memory.

Cryptographic processor device and data processing apparatus employing the same

Disclosed an oscillator circuit device includes: a resistor circuit comprising a first resistor disposed between a first supply voltage level and an output node; a resistor-capacitor circuit comprising a second resistor and at least one capacitor disposed between the output node and a second supply voltage level and connected in series, and a switch capable of discharging electric charges accumulated in the at least one capacitor; and a comparator configured to compare a voltage level to be compared obtained from the resistor circuit with a predetermined reference to allow the switch to be opened and closed according to a comparison result.

Oscillator circuit device

The present disclosure relates to a time-division multiplexing (TDM)-based multi-channel electrocardiogram measurement apparatus and method, which remove the influence of power line interference in a way to implement multiple channels by using a TDM method, remove an electrode DC offset (EDO) through a pre-charged capacitor, and periodically take a current out or supply a current. The TDM-based multi-channel electrocardiogram measurement apparatus and method robust against power line interference according to the present disclosure have advantages in that it can measure electrocardiogram by using multiple channels with low power and high integration based on TDM, can perform contactless measurement because an EDO is efficiently eliminated and high impedance is satisfied, and has a characteristic robust against power line interference.

Time-division multiplexing-based multi-channel electrocardiogram measurement apparatus robust against power line interference and electrocardiogram measurement method using the same

An exemplary embodiment of the present disclosure provides a physically unclonable function (PUF) cell capable of exhibiting a stable performance and showing an excellent repeatability while being less affected by environmental factors such as a noise, temperature, and bias voltage. The PUF cell generates an output value by combining a scheme of amplifying a threshold voltage difference and a scheme of amplifying an oscillation frequency difference. In an oscillator that generates oscillation signals of different frequencies, the frequency difference of the oscillation signals is amplified by alternately supplying bias voltages of different magnitudes generated by utilizing the threshold voltage difference to a plurality of stages in the oscillator.

Semiconductor device implementing physically unclonable function

The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

Device and method of generating nonlinear waveform signal

An electronic circuit includes first to third transistors. The first transistor has a first channel width and a first channel length and generates a first potential difference by passing an operating current based on a first operating voltage. The second transistor has a second channel width and a second channel length and generates a second potential difference based on the operating current. The third transistor generates a third potential difference based on a second operating voltage and the operating current. A sum of a level of the first operating voltage and a level of the first potential difference corresponds to a sum of a level of the second operating voltage, a level of the second potential difference, and a level of the third potential difference. The first channel width is greater than the second channel width, or the first channel length is longer than the second channel length.

Electronic circuit for generating reference voltage

Disclosed are a method and an apparatus for detecting spike event or transmitting spike event information generated in a neuromorphic chip. The apparatus for detecting spike event generated in a neuromorphic chip may detect spike event information for a plurality of neurons included in the neuromorphic chip based on a neuron group.

Neuromorphic chip and method and apparatus for detecting spike event

The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system. The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range. Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

Phase locked loop using direct digital frequency synthesizer

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Quadrature relaxation oscillator using frequency error compensation loop

The present invention relates to a successive approximation register (SAR)-type analog-digital converter (ADC), which can amplify a residual voltage without a non-linearity problem caused by an output voltage of a residual voltage amplifier, thereby performing high-resolution analog-digital conversion at low power consumption. The SAR-type ADC may include: a coarse/fine SAR conversion unit configured to receive an analog input voltage and convert the received voltage into an MSB digital signal in a coarse SAR conversion mode, and receive a feedback voltage and convert the received voltage into an LSB digital signal in a fine SAR conversion mode; and a residue integration unit configured to repeatedly amplify a residual voltage with a predetermined gain by a predetermined number of times and output the amplified voltage as a final target multiple, the residual voltage corresponding to a voltage difference between the analog input voltage and an analog voltage obtained by converting the digital signal into an analog signal.

SAR-type analog-digital converter using residue integration

An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

All digital phase locked loop

A synapse circuit to perform spike timing dependent plasticity (STDP) operation is provided. The synapse circuit includes a memristor having a resistance value, a transistor connected to the memristor, and the transistor configured to receive at least two input signals. The resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor.

Synapse circuit and neuromorphic system including the same

The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.

Injection locked digital frequency synthesizer circuit

A low-power bandgap reference voltage generator using a leakage current may include: a medium voltage generation unit configured to generate a medium voltage based on the absolute temperature, using a leakage current; a low power amplifier configured to amplify the medium voltage and outputting an operational amplification voltage; and a reference voltage output unit configured to output a reference voltage based on the operational amplification voltage at a target level.

Growing community of inventors

Pohang-si, South Korea

Jae Yoon Sim