Lg Display Co., Ltd.

Skhynix Inc.

Lg Philips Lcd Co., Inc.

Korea Institute of Industrial Technology

Gachon University of Industry-academic Cooperation Foundation

Jae Yoon Lee

Sung Joon Bae

Joon Suk Lee

Jeong Hyun Kim

Heung Lyul Cho

Jae Yong Park

Chang Wook Han

Kyung Man Kim

Young Mi Kim

Kang Ju Lee

Se Young Park

Do Hyung Kim

Kyeong Jin Kim

Yun Bok Lee

Hyung Min Lee

Hee Dong Choi

Seongjae Cho

Jang Jin Yoo

Choong Keun Yoo

Ock Hee Kim

Sang Sik Kim

Kwan Soo Kim

Do Hee Kwon

Woo Jin Nam

Woong Sik Choi

Myeong Woon Jeon

EunSeon Yu

Byung Moon Moon

Gang June Kim

Kyeong Yun Bae

Moon Ky Lee

A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.

One-transistor DRAM cell device having quantum well structure

A memory controller for performing soft decoding according to a Cell Difference Probability (CDP) calculated based on a cell distribution controls a memory device. The memory controller for controlling the memory device, the memory controller comprising: an error corrector configured to correct an error in read data received from the memory device; a command generator configured to output, in response to failing an error correction operation of the error corrector, a cell distribution detection command for detecting threshold voltage distributions of memory cells included in the memory device; and a read voltage controller configured to determine, based on cell distribution detection data that the memory device provides in response to the cell distribution detection command, a number of read voltages for a read operation to be performed in the memory device and an interval between neighboring ones among the read voltages.

Memory controller determining optimal read voltage and operating method thereof

Designs of nonvolatile memory systems and memory operations that enable allocating reliability values associated with the hard data values from memory cells and performing an error correction operation for the hard data based on the reliability values. One example of a memory system includes a nonvolatile memory device including a plurality of memory cells, and a controller suitable for obtaining hard data by performing a hard read operation based on a hard read voltage for the memory cells, and performing an error correction operation for the hard data based on reliability values.

Memory system and operating method thereof

An operation method of a data storage apparatus includes performing a first read operation using an optimal read voltage on read-failed memory cells, performing ECC decoding operation on read data, performing a second read operation using an oversampling read voltage on the read-failed memory cells when the ECC decoding operation fails, determining whether potential error memory cells which are turned on through the optimal read voltage and are turned off through the oversampling read voltage are present in the read data, determining whether neighboring memory cells which share a bit line with the potential error memory cells and are coupled to neighboring word lines are in erased state when the potential error memory cells are present, and inverting bit values corresponding to the potential error memory cells in the read data from the read-failed memory cells through the first read operation when neighboring memory cells are in erased state.

Data storage apparatus and operation method thereof

An operating method for a data storage device may include: determining a displacement value based on section memory cell numbers regarding a plurality of threshold voltage sections divided by a first read voltage and second read voltages; determining an adjustment direction based on the displacement value; adjusting at least one reliability value corresponding to at least one threshold voltage section among the threshold voltage sections, positioned in the adjustment direction from the first read voltage; and performing an error correction operation on data read from memory cells based on the first read voltage, using reliability values corresponding to the threshold voltage sections.

Non-volatile memory device and read threshold voltage adjustment method for the same

Provided are a method and apparatus for refining titanium scraps and sponge titanium, which can remove oxygen from a melt by supplying a deoxidizing gas to the surface of the melt in order to refine titanium scraps and sponge titanium. The method for refining titanium scraps and sponge titanium comprises supplying hydrogen ions and electrons in plasma to a titanium melt to remove oxygen from the titanium melt surface having an oxide layer formed thereon. In addition, the apparatus comprises: a vacuum chamber; a crucible located in the vacuum chamber and configured to perform melting by the magnetic field of an induction coil in a state in which a melt and the inner wall of the crucible; a calcium gas supply means configured to supply calcium gas from the bottom of the crucible to the space between the inner wall of the crucible and the melt.

Refining device and refining method for titanium scraps and sponge titanium using deoxidising gas

A data storage device includes a nonvolatile memory device including a target memory cell and one or more adjustment memory cells sharing bit lines with the target memory cell, one or more of the adjustment memory cell are adjacent memory cells adjacent to the target memory cells, and suitable for reading out data therefrom or storing data therein; and a controller suitable for adjusting threshold voltages of the adjustment memory cells based on threshold voltages it of the target memory cell and the adjacent memory cells.

Data storage device and operating method thereof

A data storage device may include: a nonvolatile memory device including first and second memory cells adjacent to each other; and a controller suitable for performing a distribution adjusting operation for adjusting a threshold voltage of the second memory cell based on whether a read operation on the first memory cell fails.

An organic thin film transistor and a method for manufacturing the same is disclosed, which can improve the device properties by decreasing a contact resistance which occurs in a contact area between an organic semiconductor layer and source/drain electrodes. The organic thin film transistor includes a gate electrode formed on a substrate, a gate insulation layer formed on the gate electrode, source and drain electrodes overlapped with both edges of the gate electrode and formed on the gate insulation layer, an organic semiconductor layer formed on the gate insulation layer including the source/drain electrodes, a first adhesive layer having hydrophilic properties formed between the gate insulation layer and the source/drain electrodes, and a second adhesive layer having hydrophobic properties formed between the organic semiconductor layer and the gate insulation layer.

Organic thin film transistor and method for manufacturing the same

A shadow mask and a method of fabricating an OLED display using the same is disclosed, wherein the shadow mask is not sagging, and the shadow mask includes a plurality of columns, each column including a plurality of first or second cell-forming parts, wherein the first and second cell-forming parts are alternately arranged in the columns, and the first and second cell-forming parts provided in the adjacent columns include transmission parts having the different open directions.

Shadow mask and method of fabricating organic light-emitting device using the same

An organic electroluminescent device and a method of fabricating the same are provided. The organic electroluminescent device includes a first substrate, a second substrate, a thin film transistor formed on the first substrate, a light emitting diode comprising first and second electrodes and an organic luminescent layer that are formed on the thin film transistor, and first and second passivation layers formed on the first substrate on which the light emitting diode is formed.

Organic electroluminescent device and method for fabricating the same

An organic light emitting device, which includes a first substrate, scan lines and data lines arranged on the first substrate, and at least an unit pixel comprising a R sub-pixel corresponding to a Red color, a G sub-pixel corresponding to a Green color, and a B sub-pixel corresponding to a Blue color positioned in a region on the first substrate defined by a crossing of the scan and data lines.

Organic light emitting device

An organic light emitting diode display device according to the present invention includes a first electrode on a first substrate including a first region and a second region, the second region substantially surrounding the first region; a pixel separating pattern on the first electrode in the second region; an organic light emitting pattern at least in the first region; a second electrode on the organic light emitting pattern; a contact electrode on the pixel separating pattern, the contact electrode being electrically connected to the second electrode; and a thin film transistor on the second substrate facing the first substrate, the thin film transistor being electrically connected to the contact electrode.

Organic light emitting diode display device and method of manufacturing the same

An organic electro-luminance display device includes a first substrate and a second substrate; an array element on the first substrate, the array element including at least one thin film transistor (TFT) in each sub-pixel; a first electrode on the second substrate; a buffer on the first electrode including a first buffer at an outer region partitioning each sub-pixel and a second buffer at a region including a stepped portion of the first buffer, wherein a undercut structure is formed by the first and second buffers; an organic electro-luminescent layer in each sub-pixel partitioned by the second buffer; a second electrode formed on the organic electro-luminescent layer; and a conductive spacer for electrically connecting the TFT to the second electrode.

Growing community of inventors

Yongsan-gu, South Korea

Jae Yoon Lee